From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction
Date: Mon, 19 Aug 2019 14:37:10 -0700 [thread overview]
Message-ID: <20190819213755.26175-24-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 229 ++++++++++++++++++++---------------------
target/arm/a32.decode | 44 ++++++++
target/arm/t32.decode | 44 ++++++++
3 files changed, 200 insertions(+), 117 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2764a1a637..cf03527afc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -648,99 +648,6 @@ static inline void gen_arm_shift_reg(TCGv_i32 var, int shiftop,
tcg_temp_free_i32(shift);
}
-#define PAS_OP(pfx) \
- switch (op2) { \
- case 0: gen_pas_helper(glue(pfx,add16)); break; \
- case 1: gen_pas_helper(glue(pfx,addsubx)); break; \
- case 2: gen_pas_helper(glue(pfx,subaddx)); break; \
- case 3: gen_pas_helper(glue(pfx,sub16)); break; \
- case 4: gen_pas_helper(glue(pfx,add8)); break; \
- case 7: gen_pas_helper(glue(pfx,sub8)); break; \
- }
-static void gen_arm_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_ptr tmp;
-
- switch (op1) {
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
- case 1:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(s)
- tcg_temp_free_ptr(tmp);
- break;
- case 5:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(u)
- tcg_temp_free_ptr(tmp);
- break;
-#undef gen_pas_helper
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
- case 2:
- PAS_OP(q);
- break;
- case 3:
- PAS_OP(sh);
- break;
- case 6:
- PAS_OP(uq);
- break;
- case 7:
- PAS_OP(uh);
- break;
-#undef gen_pas_helper
- }
-}
-#undef PAS_OP
-
-/* For unknown reasons Arm and Thumb-2 use arbitrarily different encodings. */
-#define PAS_OP(pfx) \
- switch (op1) { \
- case 0: gen_pas_helper(glue(pfx,add8)); break; \
- case 1: gen_pas_helper(glue(pfx,add16)); break; \
- case 2: gen_pas_helper(glue(pfx,addsubx)); break; \
- case 4: gen_pas_helper(glue(pfx,sub8)); break; \
- case 5: gen_pas_helper(glue(pfx,sub16)); break; \
- case 6: gen_pas_helper(glue(pfx,subaddx)); break; \
- }
-static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv_i32 a, TCGv_i32 b)
-{
- TCGv_ptr tmp;
-
- switch (op2) {
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
- case 0:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(s)
- tcg_temp_free_ptr(tmp);
- break;
- case 4:
- tmp = tcg_temp_new_ptr();
- tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
- PAS_OP(u)
- tcg_temp_free_ptr(tmp);
- break;
-#undef gen_pas_helper
-#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b)
- case 1:
- PAS_OP(q);
- break;
- case 2:
- PAS_OP(sh);
- break;
- case 5:
- PAS_OP(uq);
- break;
- case 6:
- PAS_OP(uh);
- break;
-#undef gen_pas_helper
- }
-}
-#undef PAS_OP
-
/*
* Generate a conditional based on ARM condition code cc.
* This is common between ARM and Aarch64 targets.
@@ -9216,6 +9123,114 @@ static bool trans_UDF(DisasContext *s, arg_UDF *a)
return true;
}
+/*
+ * Parallel addition and subtraction
+ */
+
+static bool op_par_addsub(DisasContext *s, arg_rrr *a,
+ void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
+{
+ TCGv_i32 t0, t1;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+
+ gen(t0, t0, t1);
+
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ return true;
+}
+
+static bool op_par_addsub_ge(DisasContext *s, arg_rrr *a,
+ void (*gen)(TCGv_i32, TCGv_i32,
+ TCGv_i32, TCGv_ptr))
+{
+ TCGv_i32 t0, t1;
+ TCGv_ptr ge;
+
+ if (s->thumb
+ ? !arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)
+ : !ENABLE_ARCH_6) {
+ return false;
+ }
+
+ t0 = load_reg(s, a->rn);
+ t1 = load_reg(s, a->rm);
+
+ ge = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(ge, cpu_env, offsetof(CPUARMState, GE));
+ gen(t0, t0, t1, ge);
+
+ tcg_temp_free_ptr(ge);
+ tcg_temp_free_i32(t1);
+ store_reg(s, a->rd, t0);
+ return true;
+}
+
+#define DO_PAR_ADDSUB(NAME, helper) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+{ \
+ return op_par_addsub(s, a, helper); \
+}
+
+#define DO_PAR_ADDSUB_GE(NAME, helper) \
+static bool trans_##NAME(DisasContext *s, arg_rrr *a) \
+{ \
+ return op_par_addsub_ge(s, a, helper); \
+}
+
+DO_PAR_ADDSUB_GE(SADD16, gen_helper_sadd16)
+DO_PAR_ADDSUB_GE(SASX, gen_helper_saddsubx)
+DO_PAR_ADDSUB_GE(SSAX, gen_helper_ssubaddx)
+DO_PAR_ADDSUB_GE(SSUB16, gen_helper_ssub16)
+DO_PAR_ADDSUB_GE(SADD8, gen_helper_sadd8)
+DO_PAR_ADDSUB_GE(SSUB8, gen_helper_ssub8)
+
+DO_PAR_ADDSUB_GE(UADD16, gen_helper_uadd16)
+DO_PAR_ADDSUB_GE(UASX, gen_helper_uaddsubx)
+DO_PAR_ADDSUB_GE(USAX, gen_helper_usubaddx)
+DO_PAR_ADDSUB_GE(USUB16, gen_helper_usub16)
+DO_PAR_ADDSUB_GE(UADD8, gen_helper_uadd8)
+DO_PAR_ADDSUB_GE(USUB8, gen_helper_usub8)
+
+DO_PAR_ADDSUB(QADD16, gen_helper_qadd16)
+DO_PAR_ADDSUB(QASX, gen_helper_qaddsubx)
+DO_PAR_ADDSUB(QSAX, gen_helper_qsubaddx)
+DO_PAR_ADDSUB(QSUB16, gen_helper_qsub16)
+DO_PAR_ADDSUB(QADD8, gen_helper_qadd8)
+DO_PAR_ADDSUB(QSUB8, gen_helper_qsub8)
+
+DO_PAR_ADDSUB(UQADD16, gen_helper_uqadd16)
+DO_PAR_ADDSUB(UQASX, gen_helper_uqaddsubx)
+DO_PAR_ADDSUB(UQSAX, gen_helper_uqsubaddx)
+DO_PAR_ADDSUB(UQSUB16, gen_helper_uqsub16)
+DO_PAR_ADDSUB(UQADD8, gen_helper_uqadd8)
+DO_PAR_ADDSUB(UQSUB8, gen_helper_uqsub8)
+
+DO_PAR_ADDSUB(SHADD16, gen_helper_shadd16)
+DO_PAR_ADDSUB(SHASX, gen_helper_shaddsubx)
+DO_PAR_ADDSUB(SHSAX, gen_helper_shsubaddx)
+DO_PAR_ADDSUB(SHSUB16, gen_helper_shsub16)
+DO_PAR_ADDSUB(SHADD8, gen_helper_shadd8)
+DO_PAR_ADDSUB(SHSUB8, gen_helper_shsub8)
+
+DO_PAR_ADDSUB(UHADD16, gen_helper_uhadd16)
+DO_PAR_ADDSUB(UHASX, gen_helper_uhaddsubx)
+DO_PAR_ADDSUB(UHSAX, gen_helper_uhsubaddx)
+DO_PAR_ADDSUB(UHSUB16, gen_helper_uhsub16)
+DO_PAR_ADDSUB(UHADD8, gen_helper_uhadd8)
+DO_PAR_ADDSUB(UHSUB8, gen_helper_uhsub8)
+
+#undef DO_PAR_ADDSUB
+#undef DO_PAR_ADDSUB_GE
+
/*
* Legacy decoder.
*/
@@ -9528,16 +9543,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
rs = (insn >> 8) & 0xf;
switch ((insn >> 23) & 3) {
case 0: /* Parallel add/subtract. */
- op1 = (insn >> 20) & 7;
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- sh = (insn >> 5) & 7;
- if ((op1 & 3) == 0 || sh == 5 || sh == 6)
- goto illegal_op;
- gen_arm_parallel_addsub(op1, sh, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
+ /* Done by decodetree */
+ goto illegal_op;
case 1:
if ((insn & 0x00700020) == 0) {
/* Halfword pack. */
@@ -10324,20 +10331,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
store_reg(s, rd, tmp);
break;
- case 2: /* SIMD add/subtract. */
- if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
- goto illegal_op;
- }
- op = (insn >> 20) & 7;
- shift = (insn >> 4) & 7;
- if ((op & 3) == 3 || (shift & 3) == 3)
- goto illegal_op;
- tmp = load_reg(s, rn);
- tmp2 = load_reg(s, rm);
- gen_thumb2_parallel_addsub(op, shift, tmp, tmp2);
- tcg_temp_free_i32(tmp2);
- store_reg(s, rd, tmp);
- break;
+ case 2: /* SIMD add/subtract, in decodetree */
+ goto illegal_op;
case 3: /* Other data processing. */
op = ((insn >> 17) & 0x38) | ((insn >> 4) & 7);
if (op < 4) {
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 285c08ca22..4dfd8133f7 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -410,3 +410,47 @@ BFCI ---- 0111 110 msb:5 rd:4 lsb:5 001 rn:4 &bfi
# While we could get UDEF by not including this, add the pattern for
# documentation and to conflict with any other typos in this file.
UDF 1110 0111 1111 ---- ---- ---- 1111 ----
+
+# Parallel addition and subtraction
+
+SADD16 .... 0110 0001 .... .... 1111 0001 .... @rndm
+SASX .... 0110 0001 .... .... 1111 0011 .... @rndm
+SSAX .... 0110 0001 .... .... 1111 0101 .... @rndm
+SSUB16 .... 0110 0001 .... .... 1111 0111 .... @rndm
+SADD8 .... 0110 0001 .... .... 1111 1001 .... @rndm
+SSUB8 .... 0110 0001 .... .... 1111 1111 .... @rndm
+
+QADD16 .... 0110 0010 .... .... 1111 0001 .... @rndm
+QASX .... 0110 0010 .... .... 1111 0011 .... @rndm
+QSAX .... 0110 0010 .... .... 1111 0101 .... @rndm
+QSUB16 .... 0110 0010 .... .... 1111 0111 .... @rndm
+QADD8 .... 0110 0010 .... .... 1111 1001 .... @rndm
+QSUB8 .... 0110 0010 .... .... 1111 1111 .... @rndm
+
+SHADD16 .... 0110 0011 .... .... 1111 0001 .... @rndm
+SHASX .... 0110 0011 .... .... 1111 0011 .... @rndm
+SHSAX .... 0110 0011 .... .... 1111 0101 .... @rndm
+SHSUB16 .... 0110 0011 .... .... 1111 0111 .... @rndm
+SHADD8 .... 0110 0011 .... .... 1111 1001 .... @rndm
+SHSUB8 .... 0110 0011 .... .... 1111 1111 .... @rndm
+
+UADD16 .... 0110 0101 .... .... 1111 0001 .... @rndm
+UASX .... 0110 0101 .... .... 1111 0011 .... @rndm
+USAX .... 0110 0101 .... .... 1111 0101 .... @rndm
+USUB16 .... 0110 0101 .... .... 1111 0111 .... @rndm
+UADD8 .... 0110 0101 .... .... 1111 1001 .... @rndm
+USUB8 .... 0110 0101 .... .... 1111 1111 .... @rndm
+
+UQADD16 .... 0110 0110 .... .... 1111 0001 .... @rndm
+UQASX .... 0110 0110 .... .... 1111 0011 .... @rndm
+UQSAX .... 0110 0110 .... .... 1111 0101 .... @rndm
+UQSUB16 .... 0110 0110 .... .... 1111 0111 .... @rndm
+UQADD8 .... 0110 0110 .... .... 1111 1001 .... @rndm
+UQSUB8 .... 0110 0110 .... .... 1111 1111 .... @rndm
+
+UHADD16 .... 0110 0111 .... .... 1111 0001 .... @rndm
+UHASX .... 0110 0111 .... .... 1111 0011 .... @rndm
+UHSAX .... 0110 0111 .... .... 1111 0101 .... @rndm
+UHSUB16 .... 0110 0111 .... .... 1111 0111 .... @rndm
+UHADD8 .... 0110 0111 .... .... 1111 1001 .... @rndm
+UHSUB8 .... 0110 0111 .... .... 1111 1111 .... @rndm
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 682fc5c2c4..c899c56766 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -457,3 +457,47 @@ LDAEXD_t32 1110 1000 1101 .... .... .... 1111 1111 @ldrex_d
LDA 1110 1000 1101 .... .... 1111 1010 1111 @ldrex_0
LDAB 1110 1000 1101 .... .... 1111 1000 1111 @ldrex_0
LDAH 1110 1000 1101 .... .... 1111 1001 1111 @ldrex_0
+
+# Parallel addition and subtraction
+
+SADD8 1111 1010 1000 .... 1111 .... 0000 .... @rndm
+QADD8 1111 1010 1000 .... 1111 .... 0001 .... @rndm
+SHADD8 1111 1010 1000 .... 1111 .... 0010 .... @rndm
+UADD8 1111 1010 1000 .... 1111 .... 0100 .... @rndm
+UQADD8 1111 1010 1000 .... 1111 .... 0101 .... @rndm
+UHADD8 1111 1010 1000 .... 1111 .... 0110 .... @rndm
+
+SADD16 1111 1010 1001 .... 1111 .... 0000 .... @rndm
+QADD16 1111 1010 1001 .... 1111 .... 0001 .... @rndm
+SHADD16 1111 1010 1001 .... 1111 .... 0010 .... @rndm
+UADD16 1111 1010 1001 .... 1111 .... 0100 .... @rndm
+UQADD16 1111 1010 1001 .... 1111 .... 0101 .... @rndm
+UHADD16 1111 1010 1001 .... 1111 .... 0110 .... @rndm
+
+SASX 1111 1010 1010 .... 1111 .... 0000 .... @rndm
+QASX 1111 1010 1010 .... 1111 .... 0001 .... @rndm
+SHASX 1111 1010 1010 .... 1111 .... 0010 .... @rndm
+UASX 1111 1010 1010 .... 1111 .... 0100 .... @rndm
+UQASX 1111 1010 1010 .... 1111 .... 0101 .... @rndm
+UHASX 1111 1010 1010 .... 1111 .... 0110 .... @rndm
+
+SSUB8 1111 1010 1100 .... 1111 .... 0000 .... @rndm
+QSUB8 1111 1010 1100 .... 1111 .... 0001 .... @rndm
+SHSUB8 1111 1010 1100 .... 1111 .... 0010 .... @rndm
+USUB8 1111 1010 1100 .... 1111 .... 0100 .... @rndm
+UQSUB8 1111 1010 1100 .... 1111 .... 0101 .... @rndm
+UHSUB8 1111 1010 1100 .... 1111 .... 0110 .... @rndm
+
+SSUB16 1111 1010 1101 .... 1111 .... 0000 .... @rndm
+QSUB16 1111 1010 1101 .... 1111 .... 0001 .... @rndm
+SHSUB16 1111 1010 1101 .... 1111 .... 0010 .... @rndm
+USUB16 1111 1010 1101 .... 1111 .... 0100 .... @rndm
+UQSUB16 1111 1010 1101 .... 1111 .... 0101 .... @rndm
+UHSUB16 1111 1010 1101 .... 1111 .... 0110 .... @rndm
+
+SSAX 1111 1010 1110 .... 1111 .... 0000 .... @rndm
+QSAX 1111 1010 1110 .... 1111 .... 0001 .... @rndm
+SHSAX 1111 1010 1110 .... 1111 .... 0010 .... @rndm
+USAX 1111 1010 1110 .... 1111 .... 0100 .... @rndm
+UQSAX 1111 1010 1110 .... 1111 .... 0101 .... @rndm
+UHSAX 1111 1010 1110 .... 1111 .... 0110 .... @rndm
--
2.17.1
next prev parent reply other threads:[~2019-08-19 21:57 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 21:36 [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-21 13:06 ` Philippe Mathieu-Daudé
2019-08-23 12:16 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-22 16:00 ` Peter Maydell
2019-08-22 17:21 ` Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-23 12:17 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-21 13:15 ` Philippe Mathieu-Daudé
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-23 12:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-23 11:49 ` Peter Maydell
2019-08-23 14:22 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ Richard Henderson
2019-08-23 11:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET Richard Henderson
2019-08-23 12:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-23 12:03 ` Peter Maydell
2019-08-23 14:33 ` Richard Henderson
2019-08-27 10:32 ` Peter Maydell
2019-08-27 20:01 ` Richard Henderson
2019-08-27 22:29 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-08-23 13:04 ` Peter Maydell
2019-08-23 14:45 ` Richard Henderson
2019-08-23 14:47 ` Peter Maydell
2019-08-23 14:57 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-23 14:54 ` Peter Maydell
2019-08-23 16:24 ` Richard Henderson
2019-08-27 12:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-23 15:28 ` Peter Maydell
2019-08-23 16:28 ` Richard Henderson
2019-08-27 10:44 ` Peter Maydell
2019-08-27 10:46 ` Peter Maydell
2019-08-27 11:10 ` Peter Maydell
2019-08-27 19:35 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-23 15:39 ` Peter Maydell
2019-08-23 16:30 ` Richard Henderson
2019-08-19 21:37 ` Richard Henderson [this message]
2019-08-23 15:53 ` [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-08-23 16:46 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-23 17:00 ` Peter Maydell
2019-08-23 17:15 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-23 17:05 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM Richard Henderson
2019-08-23 17:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-23 17:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-23 17:30 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc " Richard Henderson
2019-08-23 17:31 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-23 17:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC Richard Henderson
2019-08-21 13:21 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS Richard Henderson
2019-08-25 15:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-25 15:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-25 16:20 ` Peter Maydell
2019-08-25 17:28 ` Richard Henderson
2019-08-25 17:40 ` Richard Henderson
2019-08-25 20:43 ` Peter Maydell
2019-08-26 1:10 ` Richard Henderson
2019-08-26 1:36 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND Richard Henderson
2019-08-21 13:22 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-21 13:23 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-21 13:24 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch Richard Henderson
2019-08-25 16:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG Richard Henderson
2019-08-25 16:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT Richard Henderson
2019-08-25 16:33 ` Peter Maydell
2019-08-27 11:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-25 16:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-25 16:36 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-21 13:25 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-25 21:06 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-25 21:13 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-25 21:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-25 21:24 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-25 21:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-25 21:33 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-25 21:34 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-25 21:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-25 21:43 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-26 19:00 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract Richard Henderson
2019-08-26 19:08 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state Richard Henderson
2019-08-26 19:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-26 19:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints Richard Henderson
2019-08-26 19:37 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint Richard Henderson
2019-08-26 19:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop Richard Henderson
2019-08-26 19:44 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-26 19:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-26 20:38 ` Peter Maydell
2019-08-26 23:47 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-27 9:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-27 9:11 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-27 9:14 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches Richard Henderson
2019-08-27 9:34 ` Peter Maydell
2019-08-28 0:07 ` Richard Henderson
2019-09-03 8:23 ` Peter Maydell
2019-09-03 9:40 ` Aleksandar Markovic
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-27 9:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-27 9:39 ` Peter Maydell
2019-08-19 22:47 ` [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-27 12:28 ` Peter Maydell
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