From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT
Date: Mon, 19 Aug 2019 14:37:13 -0700 [thread overview]
Message-ID: <20190819213755.26175-27-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190819213755.26175-1-richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 89 ++++++++++++++++--------------------------
target/arm/a32.decode | 6 +++
target/arm/t32.decode | 9 +++++
3 files changed, 48 insertions(+), 56 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7962ac49e6..81eae286e8 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7841,6 +7841,34 @@ static bool trans_ADR(DisasContext *s, arg_ri *a)
return true;
}
+static bool trans_MOVW(DisasContext *s, arg_MOVW *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ tmp = tcg_const_i32(a->imm);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
+static bool trans_MOVT(DisasContext *s, arg_MOVW *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_6T2) {
+ return false;
+ }
+
+ tmp = load_reg(s, a->rd);
+ tcg_gen_ext16u_i32(tmp, tmp);
+ tcg_gen_ori_i32(tmp, tmp, a->imm << 16);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
/*
* Multiply and multiply accumulate
*/
@@ -9649,7 +9677,7 @@ static bool trans_UDIV(DisasContext *s, arg_rrr *a)
static void disas_arm_insn(DisasContext *s, unsigned int insn)
{
- unsigned int cond, val, op1, i, rn, rd;
+ unsigned int cond, val, op1, i, rn;
TCGv_i32 tmp;
TCGv_i32 tmp2;
TCGv_i32 addr;
@@ -9898,26 +9926,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* fall back to legacy decoder */
if ((insn & 0x0f900000) == 0x03000000) {
- if ((insn & (1 << 21)) == 0) {
- ARCH(6T2);
- rd = (insn >> 12) & 0xf;
- val = ((insn >> 4) & 0xf000) | (insn & 0xfff);
- if ((insn & (1 << 22)) == 0) {
- /* MOVW */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, val);
- } else {
- /* MOVT */
- tmp = load_reg(s, rd);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_ori_i32(tmp, tmp, val << 16);
- }
- store_reg(s, rd, tmp);
- } else {
- /* MSR (immediate) and hints */
- /* All done in decodetree. Illegal ops already signalled. */
- g_assert_not_reached();
- }
+ /* All done in decodetree. Illegal ops reach here. */
+ goto illegal_op;
} else if ((insn & 0x0f900000) == 0x01000000
&& (insn & 0x00000090) != 0x00000090) {
/* miscellaneous instructions */
@@ -10655,42 +10665,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
/*
* 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
* - Data-processing (modified immediate, plain binary immediate)
+ * All in decodetree.
*/
- if (insn & (1 << 25)) {
- /*
- * 0b1111_0x1x_xxxx_0xxx_xxxx_xxxx
- * - Data-processing (plain binary immediate)
- */
- if (insn & (1 << 24)) {
- /* Bitfield/Saturate, in decodetree */
- goto illegal_op;
- } else {
- imm = ((insn & 0x04000000) >> 15)
- | ((insn & 0x7000) >> 4) | (insn & 0xff);
- if (insn & (1 << 22)) {
- /* 16-bit immediate. */
- imm |= (insn >> 4) & 0xf000;
- if (insn & (1 << 23)) {
- /* movt */
- tmp = load_reg(s, rd);
- tcg_gen_ext16u_i32(tmp, tmp);
- tcg_gen_ori_i32(tmp, tmp, imm << 16);
- } else {
- /* movw */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, imm);
- }
- store_reg(s, rd, tmp);
- } else {
- /* Add/sub 12-bit immediate, in decodetree */
- goto illegal_op;
- }
- }
- } else {
- /* Data-processing (modified immediate) */
- /* All done in decodetree. Reach here for illegal ops. */
- goto illegal_op;
- }
+ goto illegal_op;
}
break;
case 12:
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index d7a333b90b..341882e637 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -73,6 +73,12 @@ MOV_rxri .... 000 1101 . 0000 .... ..... .. 0 .... @s_rxr_shi
BIC_rrri .... 000 1110 . .... .... ..... .. 0 .... @s_rrr_shi
MVN_rxri .... 000 1111 . 0000 .... ..... .. 0 .... @s_rxr_shi
+%imm16 16:4 0:12
+@mov16 ---- .... .... .... rd:4 ............ &ri imm=%imm16
+
+MOVW .... 0011 0000 .... .... ............ @mov16
+MOVT .... 0011 0100 .... .... ............ @mov16
+
# Data-processing (register-shifted register)
@s_rrr_shr ---- ... .... s:1 rn:4 rd:4 rs:4 . shty:2 . rm:4 \
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 677acb698d..f315fde0f4 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -150,6 +150,15 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
SUB_rri 1111 0.1 0101 0 .... 0 ... .... ........ @s0_rri_12
}
+# Move Wide
+
+%imm16_26_16_12_0 16:4 26:1 12:3 0:8
+@mov16 .... .... .... .... .... rd:4 .... .... \
+ &ri imm=%imm16_26_16_12_0
+
+MOVW 1111 0.10 0100 .... 0 ... .... ........ @mov16
+MOVT 1111 0.10 1100 .... 0 ... .... ........ @mov16
+
# Saturate, bitfield
@sat .... .... .. sh:1 . rn:4 . ... rd:4 .. . satimm:5 \
--
2.17.1
next prev parent reply other threads:[~2019-08-19 22:10 UTC|newest]
Thread overview: 167+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 21:36 [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 01/68] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 02/68] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-21 13:06 ` Philippe Mathieu-Daudé
2019-08-23 12:16 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 03/68] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-22 16:00 ` Peter Maydell
2019-08-22 17:21 ` Richard Henderson
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 04/68] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-23 12:17 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 05/68] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 06/68] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-23 12:18 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 07/68] target/arm: Simplify UMAAL Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 08/68] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-21 13:15 ` Philippe Mathieu-Daudé
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 09/68] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-23 12:20 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 10/68] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 11/68] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-23 12:21 ` Peter Maydell
2019-08-19 21:36 ` [Qemu-devel] [PATCH v2 12/68] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-23 12:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 13/68] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 14/68] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-23 12:23 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 15/68] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-23 11:49 ` Peter Maydell
2019-08-23 14:22 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 16/68] target/arm: Convert CLZ Richard Henderson
2019-08-23 11:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 17/68] target/arm: Convert ERET Richard Henderson
2019-08-23 12:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 18/68] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-23 12:03 ` Peter Maydell
2019-08-23 14:33 ` Richard Henderson
2019-08-27 10:32 ` Peter Maydell
2019-08-27 20:01 ` Richard Henderson
2019-08-27 22:29 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 19/68] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-08-23 13:04 ` Peter Maydell
2019-08-23 14:45 ` Richard Henderson
2019-08-23 14:47 ` Peter Maydell
2019-08-23 14:57 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 20/68] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-23 14:54 ` Peter Maydell
2019-08-23 16:24 ` Richard Henderson
2019-08-27 12:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 21/68] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-23 15:28 ` Peter Maydell
2019-08-23 16:28 ` Richard Henderson
2019-08-27 10:44 ` Peter Maydell
2019-08-27 10:46 ` Peter Maydell
2019-08-27 11:10 ` Peter Maydell
2019-08-27 19:35 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 22/68] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-23 15:39 ` Peter Maydell
2019-08-23 16:30 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 23/68] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-23 15:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 24/68] target/arm: Convert Packing, unpacking, saturation, and reversal Richard Henderson
2019-08-23 16:46 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 25/68] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-23 17:00 ` Peter Maydell
2019-08-23 17:15 ` Richard Henderson
2019-08-19 21:37 ` Richard Henderson [this message]
2019-08-23 17:05 ` [Qemu-devel] [PATCH v2 26/68] target/arm: Convert MOVW, MOVT Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 27/68] target/arm: Convert LDM, STM Richard Henderson
2019-08-23 17:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 28/68] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-23 17:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 29/68] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-23 17:30 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 30/68] target/arm: Diagnose base == pc " Richard Henderson
2019-08-23 17:31 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 31/68] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-23 17:53 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 32/68] target/arm: Convert SVC Richard Henderson
2019-08-21 13:21 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 33/68] target/arm: Convert RFE and SRS Richard Henderson
2019-08-25 15:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 34/68] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-25 15:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 35/68] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-25 16:20 ` Peter Maydell
2019-08-25 17:28 ` Richard Henderson
2019-08-25 17:40 ` Richard Henderson
2019-08-25 20:43 ` Peter Maydell
2019-08-26 1:10 ` Richard Henderson
2019-08-26 1:36 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 36/68] target/arm: Convert SETEND Richard Henderson
2019-08-21 13:22 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 37/68] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-21 13:23 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-21 13:24 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch Richard Henderson
2019-08-25 16:27 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG Richard Henderson
2019-08-25 16:28 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT Richard Henderson
2019-08-25 16:33 ` Peter Maydell
2019-08-27 11:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-25 16:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-25 16:36 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-21 13:25 ` Philippe Mathieu-Daudé
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-25 21:06 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-25 21:13 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 47/68] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-25 21:22 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 48/68] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-25 21:24 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 49/68] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-25 21:29 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 50/68] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-25 21:33 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-25 21:34 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-25 21:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 53/68] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-25 21:43 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-26 19:00 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract Richard Henderson
2019-08-26 19:08 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state Richard Henderson
2019-08-26 19:25 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-26 19:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints Richard Henderson
2019-08-26 19:37 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint Richard Henderson
2019-08-26 19:40 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop Richard Henderson
2019-08-26 19:44 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-26 19:52 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-26 20:38 ` Peter Maydell
2019-08-26 23:47 ` Richard Henderson
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 63/68] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-27 9:09 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 64/68] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-27 9:11 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 65/68] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-27 9:14 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 66/68] target/arm: Convert T16, long branches Richard Henderson
2019-08-27 9:34 ` Peter Maydell
2019-08-28 0:07 ` Richard Henderson
2019-09-03 8:23 ` Peter Maydell
2019-09-03 9:40 ` Aleksandar Markovic
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 67/68] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-27 9:35 ` Peter Maydell
2019-08-19 21:37 ` [Qemu-devel] [PATCH v2 68/68] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-27 9:39 ` Peter Maydell
2019-08-19 22:47 ` [Qemu-devel] [PATCH v2 00/68] target/arm: Convert aa32 base isa to decodetree no-reply
2019-08-27 12:28 ` Peter Maydell
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