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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: shorne@gmail.com
Subject: [Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3
Date: Mon, 26 Aug 2019 17:07:45 -0700	[thread overview]
Message-ID: <20190827000745.19645-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190827000745.19645-1-richard.henderson@linaro.org>

Now that the two updates from v3.1 are implemented,
update the "any" cpu to enable it.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f96a69e278..506aec6bfb 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj)
 
     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
     cpu->env.vr2 = 0;           /* No version specific id */
-    cpu->env.avr = 0x01010000;  /* Architecture v1.1 */
+    cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 
     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
-- 
2.17.1



  parent reply	other threads:[~2019-08-27  0:23 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-27  0:07 [Qemu-devel] [PATCH 00/13] target/openrisc updates Richard Henderson
2019-08-27  0:07 ` [Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write Richard Henderson
2019-08-27  4:31   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function Richard Henderson
2019-08-27  4:32   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext Richard Henderson
2019-08-27  4:32   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only Richard Henderson
2019-08-27  4:33   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init Richard Henderson
2019-08-27  4:35   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers Richard Henderson
2019-08-27  4:36   ` Stafford Horne
2019-08-27  4:59     ` Richard Henderson
2019-08-27  0:07 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s Richard Henderson
2019-08-27  4:36   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns Richard Henderson
2019-08-27  4:39   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32 Richard Henderson
2019-08-27  4:40   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons Richard Henderson
2019-08-27  4:41   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR Richard Henderson
2019-08-27  4:42   ` Stafford Horne
2019-08-27  0:07 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp Richard Henderson
2019-08-27  4:43   ` Stafford Horne
2019-08-27  0:07 ` Richard Henderson [this message]
2019-08-27  4:44   ` [Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3 Stafford Horne
2019-08-27  4:51 ` [Qemu-devel] [PATCH 00/13] target/openrisc updates Stafford Horne

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