From: Stafford Horne <shorne@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 00/13] target/openrisc updates
Date: Tue, 27 Aug 2019 13:51:16 +0900 [thread overview]
Message-ID: <20190827045116.GS24874@lianli.shorne-pla.net> (raw)
In-Reply-To: <20190827000745.19645-1-richard.henderson@linaro.org>
On Mon, Aug 26, 2019 at 05:07:32PM -0700, Richard Henderson wrote:
> The first three fix an MTTCG race on cpu_R[0], now that
> we do code generation in parallel.
>
> Then some updates to the SPRs, cpuid checks for existing
> float insns, adding the new v1.3 instructions.
>
> I've run this through the gcc testsuite as
>
> make check-gcc \
> RUNTESTFLAGS='--target_board=or1k-qemu/-mhard-float/-mdouble-float execute.exp'
>
> === gcc Summary ===
>
> # of expected passes 103979
> # of unexpected failures 26
> # of expected failures 400
> # of unresolved testcases 1
> # of unsupported tests 2539
>
> Of the 26, none are obviously floating-point related.
>
Hi Richard,
Thanks for all of that. I assume you will be taking care of upstreaming this?
FYI, I have been working on getting an old [glibc port][0] ready for upstreaming.
There still is a lot of testing and cleanup to be done. But so far the work has
uncovered 2 bugs in OpenRISC binutils and gcc. I cced you on both of those, did
you see them?
- binutils (*) : https://sourceware.org/ml/binutils/2019-08/msg00214.html
- gcc : https://gcc.gnu.org/ml/gcc-patches/2019-08/msg01549.html
* the binutils patch is already pushed upstream.
[0] https://github.com/stffrdhrn/or1k-glibc/tree/upstream-rebase
Sorry for hijacking this thread.
-Stafford
prev parent reply other threads:[~2019-08-27 4:52 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 0:07 [Qemu-devel] [PATCH 00/13] target/openrisc updates Richard Henderson
2019-08-27 0:07 ` [Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write Richard Henderson
2019-08-27 4:31 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function Richard Henderson
2019-08-27 4:32 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext Richard Henderson
2019-08-27 4:32 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only Richard Henderson
2019-08-27 4:33 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init Richard Henderson
2019-08-27 4:35 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers Richard Henderson
2019-08-27 4:36 ` Stafford Horne
2019-08-27 4:59 ` Richard Henderson
2019-08-27 0:07 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s Richard Henderson
2019-08-27 4:36 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns Richard Henderson
2019-08-27 4:39 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32 Richard Henderson
2019-08-27 4:40 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons Richard Henderson
2019-08-27 4:41 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR Richard Henderson
2019-08-27 4:42 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp Richard Henderson
2019-08-27 4:43 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3 Richard Henderson
2019-08-27 4:44 ` Stafford Horne
2019-08-27 4:51 ` Stafford Horne [this message]
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