From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: shorne@gmail.com
Subject: [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext
Date: Mon, 26 Aug 2019 17:07:35 -0700 [thread overview]
Message-ID: <20190827000745.19645-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190827000745.19645-1-richard.henderson@linaro.org>
Finish the race condition fix from the previous patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/openrisc/translate.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 3812dc4427..37e8098023 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -48,6 +48,9 @@ typedef struct DisasContext {
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
+
+ /* The temporary corresponding to register 0 for this compilation. */
+ TCGv R0;
} DisasContext;
static inline bool is_user(DisasContext *dc)
@@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc)
static TCGv cpu_sr;
static TCGv cpu_regs[32];
-static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
static TCGv cpu_ppc;
@@ -122,7 +124,6 @@ void openrisc_translate_init(void)
shadow_gpr[0][i]),
regnames[i]);
}
- cpu_R0 = cpu_regs[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
@@ -165,7 +166,11 @@ static void check_ov64s(DisasContext *dc)
static TCGv cpu_R(DisasContext *dc, int reg)
{
- return cpu_regs[reg];
+ if (reg == 0) {
+ return dc->R0;
+ } else {
+ return cpu_regs[reg];
+ }
}
/*
@@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg)
static void check_r0_write(DisasContext *dc, int reg)
{
if (unlikely(reg == 0)) {
- cpu_regs[0] = cpu_R0;
+ dc->R0 = cpu_regs[0];
}
}
@@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
to cpu_regs[0]. Since l.swa is quite often immediately followed by a
branch, don't bother reallocating; finish the TB using the "real" R0.
This also takes care of RB input across the branch. */
- cpu_regs[0] = cpu_R0;
+ dc->R0 = cpu_regs[0];
lab_fail = gen_new_label();
lab_done = gen_new_label();
@@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db, CPUState *cs)
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
if (dc->tb_flags & TB_FLAGS_R0_0) {
- cpu_regs[0] = tcg_const_tl(0);
+ dc->R0 = tcg_const_tl(0);
} else {
- cpu_regs[0] = cpu_R0;
+ dc->R0 = cpu_regs[0];
}
}
--
2.17.1
next prev parent reply other threads:[~2019-08-27 0:09 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 0:07 [Qemu-devel] [PATCH 00/13] target/openrisc updates Richard Henderson
2019-08-27 0:07 ` [Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write Richard Henderson
2019-08-27 4:31 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function Richard Henderson
2019-08-27 4:32 ` Stafford Horne
2019-08-27 0:07 ` Richard Henderson [this message]
2019-08-27 4:32 ` [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only Richard Henderson
2019-08-27 4:33 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init Richard Henderson
2019-08-27 4:35 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers Richard Henderson
2019-08-27 4:36 ` Stafford Horne
2019-08-27 4:59 ` Richard Henderson
2019-08-27 0:07 ` [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s Richard Henderson
2019-08-27 4:36 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns Richard Henderson
2019-08-27 4:39 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32 Richard Henderson
2019-08-27 4:40 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons Richard Henderson
2019-08-27 4:41 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR Richard Henderson
2019-08-27 4:42 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp Richard Henderson
2019-08-27 4:43 ` Stafford Horne
2019-08-27 0:07 ` [Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3 Richard Henderson
2019-08-27 4:44 ` Stafford Horne
2019-08-27 4:51 ` [Qemu-devel] [PATCH 00/13] target/openrisc updates Stafford Horne
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