From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v3 16/69] target/arm: Convert CLZ
Date: Wed, 28 Aug 2019 12:04:03 -0700 [thread overview]
Message-ID: <20190828190456.30315-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org>
Document our choice about the T32 CONSTRAINED UNPREDICTABLE behaviour.
This matches the undocumented choice made by the legacy decoder.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 31 +++++++++++++++----------------
target/arm/a32.decode | 4 ++++
target/arm/t32.decode | 5 +++++
3 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d60e859624..c285d4f882 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8464,6 +8464,19 @@ static bool trans_BLX_r(DisasContext *s, arg_BLX_r *a)
return true;
}
+static bool trans_CLZ(DisasContext *s, arg_CLZ *a)
+{
+ TCGv_i32 tmp;
+
+ if (!ENABLE_ARCH_5) {
+ return false;
+ }
+ tmp = load_reg(s, a->rm);
+ tcg_gen_clzi_i32(tmp, tmp, 32);
+ store_reg(s, a->rd, tmp);
+ return true;
+}
+
/*
* Legacy decoder.
*/
@@ -8752,18 +8765,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
/* MSR/MRS (banked/register) */
/* All done in decodetree. Illegal ops already signalled. */
g_assert_not_reached();
- case 0x1:
- if (op1 == 3) {
- /* clz */
- ARCH(5);
- rd = (insn >> 12) & 0xf;
- tmp = load_reg(s, rm);
- tcg_gen_clzi_i32(tmp, tmp, 32);
- store_reg(s, rd, tmp);
- } else {
- goto illegal_op;
- }
- break;
+ case 0x1: /* bx, clz */
case 0x2: /* bxj */
case 0x3: /* blx */
case 0x4: /* crc32 */
@@ -10201,13 +10203,13 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 0x08: /* rev */
case 0x09: /* rev16 */
case 0x0b: /* revsh */
- case 0x18: /* clz */
break;
case 0x10: /* sel */
if (!arm_dc_feature(s, ARM_FEATURE_THUMB_DSP)) {
goto illegal_op;
}
break;
+ case 0x18: /* clz, in decodetree */
case 0x20: /* crc32/crc32c, in decodetree */
case 0x21:
case 0x22:
@@ -10240,9 +10242,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
tcg_temp_free_i32(tmp3);
tcg_temp_free_i32(tmp2);
break;
- case 0x18: /* clz */
- tcg_gen_clzi_i32(tmp, tmp, 32);
- break;
default:
g_assert_not_reached();
}
diff --git a/target/arm/a32.decode b/target/arm/a32.decode
index 6cb9c16e2f..182f2b6725 100644
--- a/target/arm/a32.decode
+++ b/target/arm/a32.decode
@@ -29,6 +29,7 @@
&s_rrrr s rd rn rm ra
&rrrr rd rn rm ra
&rrr rd rn rm
+&rr rd rm
&r rm
&msr_reg rn r mask
&mrs_reg rd r
@@ -197,6 +198,7 @@ CRC32CW .... 0001 0100 .... .... 0010 0100 .... @rndm
%sysm 8:1 16:4
@rm ---- .... .... .... .... .... .... rm:4 &r
+@rdm ---- .... .... .... rd:4 .... .... rm:4 &rr
MRS_bank ---- 0001 0 r:1 00 .... rd:4 001. 0000 0000 &mrs_bank %sysm
MSR_bank ---- 0001 0 r:1 10 .... 1111 001. 0000 rn:4 &msr_bank %sysm
@@ -207,3 +209,5 @@ MSR_reg ---- 0001 0 r:1 10 mask:4 1111 0000 0000 rn:4 &msr_reg
BX .... 0001 0010 1111 1111 1111 0001 .... @rm
BXJ .... 0001 0010 1111 1111 1111 0010 .... @rm
BLX_r .... 0001 0010 1111 1111 1111 0011 .... @rm
+
+CLZ .... 0001 0110 1111 .... 1111 0001 .... @rdm
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
index 337706ebbe..67724efe4b 100644
--- a/target/arm/t32.decode
+++ b/target/arm/t32.decode
@@ -26,6 +26,7 @@
&s_rrrr !extern s rd rn rm ra
&rrrr !extern rd rn rm ra
&rrr !extern rd rn rm
+&rr !extern rd rm
&r !extern rm
&msr_reg !extern rn r mask
&mrs_reg !extern rd r
@@ -126,6 +127,7 @@ RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot
@rnadm .... .... .... rn:4 ra:4 rd:4 .... rm:4 &rrrr
@rn0dm .... .... .... rn:4 .... rd:4 .... rm:4 &rrrr ra=0
@rndm .... .... .... rn:4 .... rd:4 .... rm:4 &rrr
+@rdm .... .... .... .... .... rd:4 .... rm:4 &rr
{
MUL 1111 1011 0000 .... 1111 .... 0000 .... @s0_rn0dm
@@ -180,6 +182,9 @@ CRC32CB 1111 1010 1101 .... 1111 .... 1000 .... @rndm
CRC32CH 1111 1010 1101 .... 1111 .... 1001 .... @rndm
CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm
+# Note rn != rm is CONSTRAINED UNPREDICTABLE; we choose to ignore rn.
+CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
+
# Branches and miscellaneous control
%msr_sysm 4:1 8:4
--
2.17.1
next prev parent reply other threads:[~2019-08-28 19:17 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 19:03 [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 01/69] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 02/69] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 03/69] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 04/69] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 05/69] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 06/69] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 07/69] target/arm: Simplify UMAAL Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 08/69] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 09/69] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 10/69] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 11/69] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 12/69] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 13/69] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 14/69] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 15/69] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-28 19:04 ` Richard Henderson [this message]
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 17/69] target/arm: Convert ERET Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 19/69] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-09-03 10:48 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 21/69] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases Richard Henderson
2019-09-03 10:53 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 24/69] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 28/69] target/arm: Convert LDM, STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 31/69] target/arm: Diagnose base == pc " Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 34/69] target/arm: Convert RFE and SRS Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-29 16:38 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 36/69] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 37/69] target/arm: Convert SETEND Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 38/69] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 39/69] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 40/69] target/arm: Convert Table Branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 42/69] target/arm: Convert TT Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 44/69] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 47/69] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 50/69] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 53/69] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 55/69] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract Richard Henderson
2019-08-29 16:47 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state Richard Henderson
2019-09-03 10:55 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 58/69] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 60/69] target/arm: Split gen_nop_hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 61/69] target/arm: Convert T16, push and pop Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 64/69] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-29 16:44 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 65/69] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 67/69] target/arm: Convert T16, long branches Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-28 20:31 ` [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree no-reply
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