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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn
Date: Wed, 28 Aug 2019 12:04:30 -0700	[thread overview]
Message-ID: <20190828190456.30315-44-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org>

Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate.c | 79 ++----------------------------------------
 1 file changed, 3 insertions(+), 76 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 05aa998640..5bb1d13a3d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10529,9 +10529,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
 /* Translate a 32-bit thumb instruction. */
 static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
 {
-    uint32_t rn;
-    int op;
-
     /*
      * ARMv6-M supports a limited subset of Thumb2 instructions.
      * Other Thumb1 architectures allow only 32-bit
@@ -10572,34 +10569,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
     }
     /* fall back to legacy decoder */
 
-    rn = (insn >> 16) & 0xf;
     switch ((insn >> 25) & 0xf) {
     case 0: case 1: case 2: case 3:
         /* 16-bit instructions.  Should never happen.  */
         abort();
-    case 4:
-        /* All in decodetree */
-        goto illegal_op;
-    case 5:
-        /* All in decodetree */
-        goto illegal_op;
-    case 13: /* Misc data processing.  */
-        op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
-        if (op < 4 && (insn & 0xf000) != 0xf000)
-            goto illegal_op;
-        switch (op) {
-        case 0: /* Register controlled shift, in decodetree */
-        case 1: /* Sign/zero extend, in decodetree */
-        case 2: /* SIMD add/subtract, in decodetree */
-        case 3: /* Other data processing, in decodetree */
-            goto illegal_op;
-        case 4: case 5:
-            /* 32-bit multiply.  Sum of absolute differences, in decodetree */
-            goto illegal_op;
-        case 6: case 7: /* 64-bit multiply, Divide, in decodetree */
-            goto illegal_op;
-        }
-        break;
     case 6: case 7: case 14: case 15:
         /* Coprocessor.  */
         if (arm_dc_feature(s, ARM_FEATURE_M)) {
@@ -10628,6 +10601,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
                 }
 
                 if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
+                    uint32_t rn = (insn >> 16) & 0xf;
                     TCGv_i32 fptr = load_reg(s, rn);
 
                     if (extract32(insn, 20, 1)) {
@@ -10686,50 +10660,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
         }
         break;
-    case 8: case 9: case 10: case 11:
-        if (insn & (1 << 15)) {
-            /* Branches, misc control.  */
-            if (insn & 0x5000) {
-                /* Unconditional branch, in decodetree */
-                goto illegal_op;
-            } else if (((insn >> 23) & 7) == 7) {
-                /* Misc control */
-                if (insn & (1 << 13))
-                    goto illegal_op;
-
-                if (insn & (1 << 26)) {
-                    /* hvc, smc, in decodetree */
-                    goto illegal_op;
-                } else {
-                    op = (insn >> 20) & 7;
-                    switch (op) {
-                    case 0: /* msr cpsr, in decodetree  */
-                    case 1: /* msr spsr, in decodetree  */
-                        goto illegal_op;
-                    case 2: /* cps, nop-hint, in decodetree */
-                        goto illegal_op;
-                    case 3: /* Special control operations, in decodetree */
-                    case 4: /* bxj, in decodetree */
-                        goto illegal_op;
-                    case 5: /* Exception return.  */
-                    case 6: /* MRS, in decodetree */
-                    case 7: /* MSR, in decodetree */
-                        goto illegal_op;
-                    }
-                }
-            } else {
-                /* Conditional branch, in decodetree */
-                goto illegal_op;
-            }
-        } else {
-            /*
-             * 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
-             *  - Data-processing (modified immediate, plain binary immediate)
-             * All in decodetree.
-             */
-            goto illegal_op;
-        }
-        break;
     case 12:
         if ((insn & 0x01100000) == 0x01000000) {
             if (disas_neon_ls_insn(s, insn)) {
@@ -10737,14 +10667,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
             }
             break;
         }
-        /* Load/store single data item, in decodetree */
         goto illegal_op;
     default:
-        goto illegal_op;
+    illegal_op:
+        unallocated_encoding(s);
     }
-    return;
-illegal_op:
-    unallocated_encoding(s);
 }
 
 static void disas_thumb_insn(DisasContext *s, uint32_t insn)
-- 
2.17.1



  parent reply	other threads:[~2019-08-28 19:38 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28 19:03 [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 01/69] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 02/69] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 03/69] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 04/69] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 05/69] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 06/69] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 07/69] target/arm: Simplify UMAAL Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 08/69] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 09/69] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 10/69] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 11/69] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 12/69] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 13/69] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 14/69] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 15/69] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 16/69] target/arm: Convert CLZ Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 17/69] target/arm: Convert ERET Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 19/69] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-09-03 10:48   ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 21/69] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases Richard Henderson
2019-09-03 10:53   ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 24/69] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 28/69] target/arm: Convert LDM, STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 31/69] target/arm: Diagnose base == pc " Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 34/69] target/arm: Convert RFE and SRS Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-29 16:38   ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 36/69] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 37/69] target/arm: Convert SETEND Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 38/69] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 39/69] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 40/69] target/arm: Convert Table Branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 42/69] target/arm: Convert TT Richard Henderson
2019-08-28 19:04 ` Richard Henderson [this message]
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 44/69] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 47/69] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 50/69] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 53/69] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 55/69] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract Richard Henderson
2019-08-29 16:47   ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state Richard Henderson
2019-09-03 10:55   ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 58/69] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 60/69] target/arm: Split gen_nop_hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 61/69] target/arm: Convert T16, push and pop Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 64/69] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-29 16:44   ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 65/69] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 67/69] target/arm: Convert T16, long branches Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-28 20:31 ` [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree no-reply

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