From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [Qemu-devel] [PATCH v3 46/69] target/arm: Convert T16 data-processing (two low regs)
Date: Wed, 28 Aug 2019 12:04:33 -0700 [thread overview]
Message-ID: <20190828190456.30315-47-richard.henderson@linaro.org> (raw)
In-Reply-To: <20190828190456.30315-1-richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 152 ++---------------------------------------
target/arm/t16.decode | 36 ++++++++++
2 files changed, 43 insertions(+), 145 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 106ef08ada..6e841c346f 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -445,13 +445,6 @@ static inline void gen_logic_CC(TCGv_i32 var)
tcg_gen_mov_i32(cpu_ZF, var);
}
-/* T0 += T1 + CF. */
-static void gen_adc(TCGv_i32 t0, TCGv_i32 t1)
-{
- tcg_gen_add_i32(t0, t0, t1);
- tcg_gen_add_i32(t0, t0, cpu_CF);
-}
-
/* dest = T0 + T1 + CF. */
static void gen_add_carry(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
{
@@ -7527,6 +7520,11 @@ static int t32_branch24(DisasContext *s, int x)
return x << 1;
}
+static int t16_setflags(DisasContext *s)
+{
+ return s->condexec_mask == 0;
+}
+
/*
* Include the generated decoders.
*/
@@ -10838,145 +10836,9 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
/*
* 0b0100_00xx_xxxx_xxxx
- * - Data-processing (two low registers)
+ * - Data-processing (two low registers), in decodetree
*/
- rd = insn & 7;
- rm = (insn >> 3) & 7;
- op = (insn >> 6) & 0xf;
- if (op == 2 || op == 3 || op == 4 || op == 7) {
- /* the shift/rotate ops want the operands backwards */
- val = rm;
- rm = rd;
- rd = val;
- val = 1;
- } else {
- val = 0;
- }
-
- if (op == 9) { /* neg */
- tmp = tcg_temp_new_i32();
- tcg_gen_movi_i32(tmp, 0);
- } else if (op != 0xf) { /* mvn doesn't read its first operand */
- tmp = load_reg(s, rd);
- } else {
- tmp = NULL;
- }
-
- tmp2 = load_reg(s, rm);
- switch (op) {
- case 0x0: /* and */
- tcg_gen_and_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0x1: /* eor */
- tcg_gen_xor_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0x2: /* lsl */
- if (s->condexec_mask) {
- gen_shl(tmp2, tmp2, tmp);
- } else {
- gen_helper_shl_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x3: /* lsr */
- if (s->condexec_mask) {
- gen_shr(tmp2, tmp2, tmp);
- } else {
- gen_helper_shr_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x4: /* asr */
- if (s->condexec_mask) {
- gen_sar(tmp2, tmp2, tmp);
- } else {
- gen_helper_sar_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x5: /* adc */
- if (s->condexec_mask) {
- gen_adc(tmp, tmp2);
- } else {
- gen_adc_CC(tmp, tmp, tmp2);
- }
- break;
- case 0x6: /* sbc */
- if (s->condexec_mask) {
- gen_sub_carry(tmp, tmp, tmp2);
- } else {
- gen_sbc_CC(tmp, tmp, tmp2);
- }
- break;
- case 0x7: /* ror */
- if (s->condexec_mask) {
- tcg_gen_andi_i32(tmp, tmp, 0x1f);
- tcg_gen_rotr_i32(tmp2, tmp2, tmp);
- } else {
- gen_helper_ror_cc(tmp2, cpu_env, tmp2, tmp);
- gen_logic_CC(tmp2);
- }
- break;
- case 0x8: /* tst */
- tcg_gen_and_i32(tmp, tmp, tmp2);
- gen_logic_CC(tmp);
- rd = 16;
- break;
- case 0x9: /* neg */
- if (s->condexec_mask)
- tcg_gen_neg_i32(tmp, tmp2);
- else
- gen_sub_CC(tmp, tmp, tmp2);
- break;
- case 0xa: /* cmp */
- gen_sub_CC(tmp, tmp, tmp2);
- rd = 16;
- break;
- case 0xb: /* cmn */
- gen_add_CC(tmp, tmp, tmp2);
- rd = 16;
- break;
- case 0xc: /* orr */
- tcg_gen_or_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xd: /* mul */
- tcg_gen_mul_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xe: /* bic */
- tcg_gen_andc_i32(tmp, tmp, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp);
- break;
- case 0xf: /* mvn */
- tcg_gen_not_i32(tmp2, tmp2);
- if (!s->condexec_mask)
- gen_logic_CC(tmp2);
- val = 1;
- rm = rd;
- break;
- }
- if (rd != 16) {
- if (val) {
- store_reg(s, rm, tmp2);
- if (op != 0xf)
- tcg_temp_free_i32(tmp);
- } else {
- store_reg(s, rd, tmp);
- tcg_temp_free_i32(tmp2);
- }
- } else {
- tcg_temp_free_i32(tmp);
- tcg_temp_free_i32(tmp2);
- }
- break;
+ goto illegal_op;
case 5:
/* load/store register offset. */
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index e954f61fe4..44e7250c55 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -18,3 +18,39 @@
#
# This file is processed by scripts/decodetree.py
#
+
+&s_rrr_shi !extern s rd rn rm shim shty
+&s_rrr_shr !extern s rn rd rm rs shty
+&s_rri_rot !extern s rn rd imm rot
+&s_rrrr !extern s rd rn rm ra
+
+# Set S if the instruction is outside of an IT block.
+%s !function=t16_setflags
+
+# Data-processing (two low registers)
+
+%reg_0 0:3
+
+@lll_noshr ...... .... rm:3 rd:3 \
+ &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
+@xll_noshr ...... .... rm:3 rn:3 \
+ &s_rrr_shi s=1 rd=0 shim=0 shty=0
+@lxl_shr ...... .... rs:3 rd:3 \
+ &s_rrr_shr %s rm=%reg_0 rn=0
+
+AND_rrri 010000 0000 ... ... @lll_noshr
+EOR_rrri 010000 0001 ... ... @lll_noshr
+MOV_rxrr 010000 0010 ... ... @lxl_shr shty=0 # LSL
+MOV_rxrr 010000 0011 ... ... @lxl_shr shty=1 # LSR
+MOV_rxrr 010000 0100 ... ... @lxl_shr shty=2 # ASR
+ADC_rrri 010000 0101 ... ... @lll_noshr
+SBC_rrri 010000 0110 ... ... @lll_noshr
+MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
+TST_xrri 010000 1000 ... ... @xll_noshr
+RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
+CMP_xrri 010000 1010 ... ... @xll_noshr
+CMN_xrri 010000 1011 ... ... @xll_noshr
+ORR_rrri 010000 1100 ... ... @lll_noshr
+MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
+BIC_rrri 010000 1110 ... ... @lll_noshr
+MVN_rxri 010000 1111 ... ... @lll_noshr
--
2.17.1
next prev parent reply other threads:[~2019-08-28 20:03 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 19:03 [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 01/69] target/arm: Use store_reg_from_load in thumb2 code Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 02/69] target/arm: Add stubs for aa32 decodetree Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 03/69] target/arm: Convert Data Processing (register) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 04/69] target/arm: Convert Data Processing (reg-shifted-reg) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 05/69] target/arm: Convert Data Processing (immediate) Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 06/69] target/arm: Convert multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 07/69] target/arm: Simplify UMAAL Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 08/69] target/arm: Convert Saturating addition and subtraction Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 09/69] target/arm: Convert Halfword multiply and multiply accumulate Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 10/69] target/arm: Simplify op_smlaxxx for SMLAL* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 11/69] target/arm: Simplify op_smlawx for SMLAW* Richard Henderson
2019-08-28 19:03 ` [Qemu-devel] [PATCH v3 12/69] target/arm: Convert MSR (immediate) and hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 13/69] target/arm: Convert MRS/MSR (banked, register) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 14/69] target/arm: Convert Cyclic Redundancy Check Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 15/69] target/arm: Convert BX, BXJ, BLX (register) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 16/69] target/arm: Convert CLZ Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 17/69] target/arm: Convert ERET Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 19/69] target/arm: Convert T32 ADDW/SUBW Richard Henderson
2019-09-03 10:48 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 21/69] target/arm: Convert Synchronization primitives Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases Richard Henderson
2019-09-03 10:53 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 24/69] target/arm: Convert Parallel addition and subtraction Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 28/69] target/arm: Convert LDM, STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7 Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 31/69] target/arm: Diagnose base == pc " Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 33/69] target/arm: Convert SVC Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 34/69] target/arm: Convert RFE and SRS Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 35/69] target/arm: Convert Clear-Exclusive, Barriers Richard Henderson
2019-08-29 16:38 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 36/69] target/arm: Convert CPS (privileged) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 37/69] target/arm: Convert SETEND Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 38/69] target/arm: Convert PLI, PLD, PLDW Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 39/69] target/arm: Convert Unallocated memory hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 40/69] target/arm: Convert Table Branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 42/69] target/arm: Convert TT Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 43/69] target/arm: Simplify disas_thumb2_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 44/69] target/arm: Simplify disas_arm_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 45/69] target/arm: Add skeleton for T16 decodetree Richard Henderson
2019-08-28 19:04 ` Richard Henderson [this message]
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 47/69] target/arm: Convert T16 load/store (register offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 48/69] target/arm: Convert T16 load/store (immediate offset) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 49/69] target/arm: Convert T16 add pc/sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 50/69] target/arm: Convert T16 load/store multiple Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 52/69] target/arm: Convert T16 one low register and immediate Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 53/69] target/arm: Convert T16 branch and exchange Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 54/69] target/arm: Convert T16 add, compare, move (two high registers) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 55/69] target/arm: Convert T16 adjust sp (immediate) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 56/69] target/arm: Convert T16, extract Richard Henderson
2019-08-29 16:47 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 57/69] target/arm: Convert T16, Change processor state Richard Henderson
2019-09-03 10:55 ` Peter Maydell
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 58/69] target/arm: Convert T16, Reverse bytes Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 59/69] target/arm: Convert T16, nop hints Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 60/69] target/arm: Split gen_nop_hint Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 61/69] target/arm: Convert T16, push and pop Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 62/69] target/arm: Convert T16, Conditional branches, Supervisor call Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 64/69] target/arm: Convert T16, shift immediate Richard Henderson
2019-08-29 16:44 ` Philippe Mathieu-Daudé
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 65/69] target/arm: Convert T16, load (literal) Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 66/69] target/arm: Convert T16, Unconditional branch Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 67/69] target/arm: Convert T16, long branches Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 68/69] target/arm: Clean up disas_thumb_insn Richard Henderson
2019-08-28 19:04 ` [Qemu-devel] [PATCH v3 69/69] target/arm: Inline gen_bx_im into callers Richard Henderson
2019-08-28 20:31 ` [Qemu-devel] [PATCH v3 00/69] target/arm: Convert aa32 base isa to decodetree no-reply
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