From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
ilippe=20Mathieu-Daud=C3=A9?= <philmd@redhat.com>
Subject: [PULL 13/18] riscv/virt: Jump to pflash if specified
Date: Mon, 28 Oct 2019 08:48:57 -0700 [thread overview]
Message-ID: <20191028154902.32491-14-palmer@sifive.com> (raw)
In-Reply-To: <20191028154902.32491-1-palmer@sifive.com>
From: Alistair Francis <alistair.francis@wdc.com>
If the user supplied pflash to QEMU then change the reset code to jump
to the pflash base address instead of the DRAM base address.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/virt.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b2156abd6c..cc8f311e6b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -443,6 +443,7 @@ static void riscv_virt_board_init(MachineState *machine)
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
char *plic_hart_config;
size_t plic_hart_config_len;
+ target_ulong start_addr = memmap[VIRT_DRAM].base;
int i;
unsigned int smp_cpus = machine->smp.cpus;
@@ -489,6 +490,14 @@ static void riscv_virt_board_init(MachineState *machine)
}
}
+ if (drive_get(IF_PFLASH, 0, 0)) {
+ /*
+ * Pflash was supplied, let's overwrite the address we jump to after
+ * reset to the base of the flash.
+ */
+ start_addr = virt_memmap[VIRT_FLASH].base;
+ }
+
/* reset vector */
uint32_t reset_vec[8] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
@@ -501,7 +510,7 @@ static void riscv_virt_board_init(MachineState *machine)
#endif
0x00028067, /* jr t0 */
0x00000000,
- memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */
+ start_addr, /* start: .dword */
0x00000000,
/* dtb: */
};
--
2.21.0
next prev parent reply other threads:[~2019-10-28 16:54 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 15:48 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Palmer Dabbelt
2019-10-28 15:48 ` [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode Palmer Dabbelt
2019-10-28 15:48 ` [PULL 02/18] RISC-V: Handle bus errors in the page table walker Palmer Dabbelt
2019-10-28 15:48 ` [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed Palmer Dabbelt
2019-10-28 15:48 ` [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes Palmer Dabbelt
2019-10-28 15:48 ` [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node Palmer Dabbelt
2019-10-28 15:48 ` [PULL 06/18] linux-user/riscv: Propagate fault address Palmer Dabbelt
2019-10-28 15:48 ` [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory Palmer Dabbelt
2019-10-28 15:48 ` [PULL 08/18] riscv/sifive_u: Add QSPI memory region Palmer Dabbelt
2019-10-28 15:48 ` [PULL 09/18] riscv/sifive_u: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 10/18] riscv/sifive_u: Add the start-in-flash property Palmer Dabbelt
2019-10-28 15:48 ` [PULL 11/18] riscv/virt: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 12/18] riscv/virt: Add the PFlash CFI01 device Palmer Dabbelt
2019-10-28 15:48 ` Palmer Dabbelt [this message]
2019-10-28 15:48 ` [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs Palmer Dabbelt
2019-10-28 15:48 ` [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads Palmer Dabbelt
2019-10-28 15:49 ` [PULL 16/18] target/riscv: Make the priv register writable by GDB Palmer Dabbelt
2019-10-28 15:49 ` [PULL 17/18] riscv/boot: Fix possible memory leak Palmer Dabbelt
2019-10-28 15:49 ` [PULL 18/18] target/riscv: PMP violation due to wrong size parameter Palmer Dabbelt
2019-10-29 8:37 ` [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Peter Maydell
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