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From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair.francis@wdc.com>,
	Bin Meng <bmeng.cn@gmail.com>,
	qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	Palmer Dabbelt <palmer@sifive.com>
Subject: [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes
Date: Mon, 28 Oct 2019 08:48:48 -0700	[thread overview]
Message-ID: <20191028154902.32491-5-palmer@sifive.com> (raw)
In-Reply-To: <20191028154902.32491-1-palmer@sifive.com>

From: Bin Meng <bmeng.cn@gmail.com>

The "clock-frequency" property of cpu nodes isn't required. Drop it.

This is to keep in sync with Linux kernel commit below:
https://patchwork.kernel.org/patch/11133031/

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 hw/riscv/sifive_u.c         | 2 --
 hw/riscv/spike.c            | 2 --
 hw/riscv/virt.c             | 2 --
 include/hw/riscv/sifive_u.h | 1 -
 include/hw/riscv/spike.h    | 4 ----
 include/hw/riscv/virt.h     | 4 ----
 6 files changed, 15 deletions(-)

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 9f8e84bf2e..02dd76176e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -151,8 +151,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
         char *isa;
         qemu_fdt_add_subnode(fdt, nodename);
-        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-                              SIFIVE_U_CLOCK_FREQ);
         /* cpu 0 is the management hart that does not have mmu */
         if (cpu != 0) {
             qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d60415d190..8bbffbcd0f 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -102,8 +102,6 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
         qemu_fdt_add_subnode(fdt, nodename);
-        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-                              SPIKE_CLOCK_FREQ);
         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d36f5625ec..13030619d4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -161,8 +161,6 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
         qemu_fdt_add_subnode(fdt, nodename);
-        qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
-                              VIRT_CLOCK_FREQ);
         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index e4df298c23..4850805ee7 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -75,7 +75,6 @@ enum {
 };
 
 enum {
-    SIFIVE_U_CLOCK_FREQ = 1000000000,
     SIFIVE_U_HFCLK_FREQ = 33333333,
     SIFIVE_U_RTCCLK_FREQ = 1000000
 };
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index 03d870363c..dc770421bc 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -38,10 +38,6 @@ enum {
     SPIKE_DRAM
 };
 
-enum {
-    SPIKE_CLOCK_FREQ = 1000000000
-};
-
 #if defined(TARGET_RISCV32)
 #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 6e5fbe5d3b..68978a13e8 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -55,10 +55,6 @@ enum {
     VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
 };
 
-enum {
-    VIRT_CLOCK_FREQ = 1000000000
-};
-
 #define VIRT_PLIC_HART_CONFIG "MS"
 #define VIRT_PLIC_NUM_SOURCES 127
 #define VIRT_PLIC_NUM_PRIORITIES 7
-- 
2.21.0



  parent reply	other threads:[~2019-10-28 16:06 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 15:48 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Palmer Dabbelt
2019-10-28 15:48 ` [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode Palmer Dabbelt
2019-10-28 15:48 ` [PULL 02/18] RISC-V: Handle bus errors in the page table walker Palmer Dabbelt
2019-10-28 15:48 ` [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed Palmer Dabbelt
2019-10-28 15:48 ` Palmer Dabbelt [this message]
2019-10-28 15:48 ` [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node Palmer Dabbelt
2019-10-28 15:48 ` [PULL 06/18] linux-user/riscv: Propagate fault address Palmer Dabbelt
2019-10-28 15:48 ` [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory Palmer Dabbelt
2019-10-28 15:48 ` [PULL 08/18] riscv/sifive_u: Add QSPI memory region Palmer Dabbelt
2019-10-28 15:48 ` [PULL 09/18] riscv/sifive_u: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 10/18] riscv/sifive_u: Add the start-in-flash property Palmer Dabbelt
2019-10-28 15:48 ` [PULL 11/18] riscv/virt: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 12/18] riscv/virt: Add the PFlash CFI01 device Palmer Dabbelt
2019-10-28 15:48 ` [PULL 13/18] riscv/virt: Jump to pflash if specified Palmer Dabbelt
2019-10-28 15:48 ` [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs Palmer Dabbelt
2019-10-28 15:48 ` [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads Palmer Dabbelt
2019-10-28 15:49 ` [PULL 16/18] target/riscv: Make the priv register writable by GDB Palmer Dabbelt
2019-10-28 15:49 ` [PULL 17/18] riscv/boot: Fix possible memory leak Palmer Dabbelt
2019-10-28 15:49 ` [PULL 18/18] target/riscv: PMP violation due to wrong size parameter Palmer Dabbelt
2019-10-29  8:37 ` [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Peter Maydell

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