From: Palmer Dabbelt <palmer@sifive.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-riscv@nongnu.org, Palmer Dabbelt <palmer@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>,
ilippe=20Mathieu-Daud=C3=A9?= <philmd@redhat.com>
Subject: [PULL 17/18] riscv/boot: Fix possible memory leak
Date: Mon, 28 Oct 2019 08:49:01 -0700 [thread overview]
Message-ID: <20191028154902.32491-18-palmer@sifive.com> (raw)
In-Reply-To: <20191028154902.32491-1-palmer@sifive.com>
From: Alistair Francis <alistair.francis@wdc.com>
Coverity (CID 1405786) thinks that there is a possible memory leak as
we don't guarantee that the memory allocated from riscv_find_firmware()
is freed. This is a false positive, but let's tidy up the code to fix
the warning.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
hw/riscv/boot.c | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 2e92fb0680..7fee98d2f8 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -38,7 +38,7 @@ void riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr)
{
- char *firmware_filename;
+ char *firmware_filename = NULL;
if (!machine->firmware) {
/*
@@ -70,14 +70,11 @@ void riscv_find_and_load_firmware(MachineState *machine,
* if no -bios option is set without breaking anything.
*/
firmware_filename = riscv_find_firmware(default_machine_firmware);
- } else {
- firmware_filename = machine->firmware;
- if (strcmp(firmware_filename, "none")) {
- firmware_filename = riscv_find_firmware(firmware_filename);
- }
+ } else if (strcmp(machine->firmware, "none")) {
+ firmware_filename = riscv_find_firmware(machine->firmware);
}
- if (strcmp(firmware_filename, "none")) {
+ if (firmware_filename) {
/* If not "none" load the firmware */
riscv_load_firmware(firmware_filename, firmware_load_addr);
g_free(firmware_filename);
--
2.21.0
next prev parent reply other threads:[~2019-10-28 17:14 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 15:48 [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Palmer Dabbelt
2019-10-28 15:48 ` [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode Palmer Dabbelt
2019-10-28 15:48 ` [PULL 02/18] RISC-V: Handle bus errors in the page table walker Palmer Dabbelt
2019-10-28 15:48 ` [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed Palmer Dabbelt
2019-10-28 15:48 ` [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes Palmer Dabbelt
2019-10-28 15:48 ` [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node Palmer Dabbelt
2019-10-28 15:48 ` [PULL 06/18] linux-user/riscv: Propagate fault address Palmer Dabbelt
2019-10-28 15:48 ` [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory Palmer Dabbelt
2019-10-28 15:48 ` [PULL 08/18] riscv/sifive_u: Add QSPI memory region Palmer Dabbelt
2019-10-28 15:48 ` [PULL 09/18] riscv/sifive_u: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 10/18] riscv/sifive_u: Add the start-in-flash property Palmer Dabbelt
2019-10-28 15:48 ` [PULL 11/18] riscv/virt: Manually define the machine Palmer Dabbelt
2019-10-28 15:48 ` [PULL 12/18] riscv/virt: Add the PFlash CFI01 device Palmer Dabbelt
2019-10-28 15:48 ` [PULL 13/18] riscv/virt: Jump to pflash if specified Palmer Dabbelt
2019-10-28 15:48 ` [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs Palmer Dabbelt
2019-10-28 15:48 ` [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads Palmer Dabbelt
2019-10-28 15:49 ` [PULL 16/18] target/riscv: Make the priv register writable by GDB Palmer Dabbelt
2019-10-28 15:49 ` Palmer Dabbelt [this message]
2019-10-28 15:49 ` [PULL 18/18] target/riscv: PMP violation due to wrong size parameter Palmer Dabbelt
2019-10-29 8:37 ` [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 2 Peter Maydell
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