From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Stefano Stabellini" <sstabellini@kernel.org>,
"Paul Durrant" <paul@xen.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Aleksandar Markovic" <amarkovic@wavecomp.com>,
"open list:X86 Xen CPUs" <xen-devel@lists.xenproject.org>,
"Anthony Perard" <anthony.perard@citrix.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@rt-rk.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PULL 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
Date: Mon, 28 Oct 2019 17:34:42 +0100 [thread overview]
Message-ID: <20191028163447.18541-16-philmd@redhat.com> (raw)
In-Reply-To: <20191028163447.18541-1-philmd@redhat.com>
The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.
Acked-by: Paul Durrant <paul@xen.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/xen/xen-hvm.c | 5 +++--
hw/mips/gt64xxx_pci.c | 4 ++--
hw/pci-host/piix.c | 9 ++++-----
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 95f23a263c..82ece6b9e7 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
v = 0;
}
v &= 0xf;
- if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
- xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+ if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+ xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
}
}
}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[0x60 + irq_num];
+ pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[0x60 + i]) {
+ if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
pic_level |= pci_irq_levels[i];
}
}
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 6548d9a4b5..390fb9ceba 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS 128ULL
-#define PIIX_PIRQC 0x60
typedef struct PIIX3State {
PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQC + pin];
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
int pic_irq;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index e49d4a6bbe..094508b928 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
--
2.21.0
next prev parent reply other threads:[~2019-10-28 18:10 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 16:34 [PULL 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 02/20] piix4: Add the Reset Control Register Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 03/20] piix4: Add an i8259 Interrupt Controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 04/20] Revert "irq: introduce qemu_irq_proxy()" Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 05/20] piix4: Rename PIIX4 object to piix4-isa Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 06/20] piix4: Add an i8257 DMA Controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 07/20] piix4: Add an i8254 PIT " Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 08/20] piix4: Add a MC146818 RTC " Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 10/20] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 11/20] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 12/20] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 13/20] hw/pci-host/piix: Extract piix3_create() Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition Philippe Mathieu-Daudé
2019-10-28 16:34 ` Philippe Mathieu-Daudé [this message]
2019-10-28 16:34 ` [PULL 16/20] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 17/20] hw/pci-host/piix: Fix code style issues Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 18/20] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 19/20] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' Philippe Mathieu-Daudé
2019-10-28 16:34 ` [PULL 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces Philippe Mathieu-Daudé
2019-10-28 22:44 ` [PULL 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge no-reply
2019-10-29 1:58 ` no-reply
2019-10-29 3:19 ` no-reply
2019-10-29 5:16 ` no-reply
2019-10-29 5:18 ` Aleksandar Markovic
2019-10-29 17:04 ` Philippe Mathieu-Daudé
2019-10-29 22:10 ` Aleksandar Markovic
2019-10-30 6:15 ` Peter Maydell
2019-10-30 9:44 ` Philippe Mathieu-Daudé
2019-11-02 20:28 ` Philippe Mathieu-Daudé
2019-11-02 20:56 ` Philippe Mathieu-Daudé
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