qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 28/46] target/arm: Implement UAO semantics
Date: Thu, 13 Feb 2020 14:41:27 +0000	[thread overview]
Message-ID: <20200213144145.818-29-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200213144145.818-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

We need only override the current condition under which
TBFLAG_A64.UNPRIV is set.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 41 +++++++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 20 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 11a5f0be52f..366dbcf460d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12198,28 +12198,29 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
     }
 
     /* Compute the condition for using AccType_UNPRIV for LDTR et al. */
-    /* TODO: ARMv8.2-UAO */
-    switch (mmu_idx) {
-    case ARMMMUIdx_E10_1:
-    case ARMMMUIdx_E10_1_PAN:
-    case ARMMMUIdx_SE10_1:
-    case ARMMMUIdx_SE10_1_PAN:
-        /* TODO: ARMv8.3-NV */
-        flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
-        break;
-    case ARMMMUIdx_E20_2:
-    case ARMMMUIdx_E20_2_PAN:
-        /* TODO: ARMv8.4-SecEL2 */
-        /*
-         * Note that E20_2 is gated by HCR_EL2.E2H == 1, but E20_0 is
-         * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
-         */
-        if (env->cp15.hcr_el2 & HCR_TGE) {
+    if (!(env->pstate & PSTATE_UAO)) {
+        switch (mmu_idx) {
+        case ARMMMUIdx_E10_1:
+        case ARMMMUIdx_E10_1_PAN:
+        case ARMMMUIdx_SE10_1:
+        case ARMMMUIdx_SE10_1_PAN:
+            /* TODO: ARMv8.3-NV */
             flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+            break;
+        case ARMMMUIdx_E20_2:
+        case ARMMMUIdx_E20_2_PAN:
+            /* TODO: ARMv8.4-SecEL2 */
+            /*
+             * Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
+             * gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
+             */
+            if (env->cp15.hcr_el2 & HCR_TGE) {
+                flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+            }
+            break;
+        default:
+            break;
         }
-        break;
-    default:
-        break;
     }
 
     return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
-- 
2.20.1



  parent reply	other threads:[~2020-02-13 14:56 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-13 14:40 [PULL 00/46] target-arm queue Peter Maydell
2020-02-13 14:41 ` [PULL 01/46] i.MX: Fix inverted register bits in wdt code Peter Maydell
2020-02-13 14:41 ` [PULL 02/46] i.MX: Add support for WDT on i.MX6 Peter Maydell
2020-02-13 14:41 ` [PULL 03/46] bios-tables-test: prepare to change ARM virt ACPI DSDT Peter Maydell
2020-02-13 14:41 ` [PULL 04/46] arm/virt/acpi: remove meaningless sub device "RP0" from PCI0 Peter Maydell
2020-02-13 14:41 ` [PULL 05/46] arm/virt/acpi: remove _ADR from devices identified by _HID Peter Maydell
2020-02-13 14:41 ` [PULL 06/46] arm/acpi: fix PCI _PRT definition Peter Maydell
2020-02-13 14:41 ` [PULL 07/46] arm/acpi: fix duplicated _UID of PCI interrupt link devices Peter Maydell
2020-02-13 14:41 ` [PULL 08/46] arm/acpi: simplify the description of PCI _CRS Peter Maydell
2020-02-13 14:41 ` [PULL 09/46] virt/acpi: update golden masters for DSDT update Peter Maydell
2020-02-13 14:41 ` [PULL 10/46] target/arm: Add arm_mmu_idx_is_stage1_of_2 Peter Maydell
2020-02-13 14:41 ` [PULL 11/46] target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled Peter Maydell
2020-02-13 14:41 ` [PULL 12/46] target/arm: Add isar_feature tests for PAN + ATS1E1 Peter Maydell
2020-02-13 14:41 ` [PULL 13/46] target/arm: Move LOR regdefs to file scope Peter Maydell
2020-02-13 14:41 ` [PULL 14/46] target/arm: Split out aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 15/46] target/arm: Mask CPSR_J when Jazelle is not enabled Peter Maydell
2020-02-13 14:41 ` [PULL 16/46] target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 17/46] target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return Peter Maydell
2020-02-13 14:41 ` [PULL 18/46] target/arm: Remove CPSR_RESERVED Peter Maydell
2020-02-13 14:41 ` [PULL 19/46] target/arm: Introduce aarch64_pstate_valid_mask Peter Maydell
2020-02-13 14:41 ` [PULL 20/46] target/arm: Update MSR access for PAN Peter Maydell
2020-02-13 14:41 ` [PULL 21/46] target/arm: Update arm_mmu_idx_el " Peter Maydell
2020-02-13 14:41 ` [PULL 22/46] target/arm: Enforce PAN semantics in get_S1prot Peter Maydell
2020-02-13 14:41 ` [PULL 23/46] target/arm: Set PAN bit as required on exception entry Peter Maydell
2020-02-13 14:41 ` [PULL 24/46] target/arm: Implement ATS1E1 system registers Peter Maydell
2020-02-13 14:41 ` [PULL 25/46] target/arm: Enable ARMv8.2-ATS1E1 in -cpu max Peter Maydell
2020-02-13 14:41 ` [PULL 26/46] target/arm: Add ID_AA64MMFR2_EL1 Peter Maydell
2020-02-13 14:41 ` [PULL 27/46] target/arm: Update MSR access to UAO Peter Maydell
2020-02-13 14:41 ` Peter Maydell [this message]
2020-02-13 14:41 ` [PULL 29/46] target/arm: Enable ARMv8.2-UAO in -cpu max Peter Maydell
2020-02-13 14:41 ` [PULL 30/46] hw/arm: ast2400/ast2500: Wire up EHCI controllers Peter Maydell
2020-02-13 14:41 ` [PULL 31/46] hw/arm: ast2600: " Peter Maydell
2020-02-13 14:41 ` [PULL 32/46] hw/char/exynos4210_uart: Fix memleaks in exynos4210_uart_init Peter Maydell
2020-02-13 14:41 ` [PULL 33/46] hw/arm/raspi: Use BCM2708 machine type with pre Device Tree kernels Peter Maydell
2020-02-13 14:41 ` [PULL 34/46] hw/arm/raspi: Correct the board descriptions Peter Maydell
2020-02-13 14:41 ` [PULL 35/46] hw/arm/raspi: Extract the version from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 36/46] hw/arm/raspi: Extract the RAM size " Peter Maydell
2020-02-13 14:41 ` [PULL 37/46] hw/arm/raspi: Extract the processor type " Peter Maydell
2020-02-13 14:41 ` [PULL 38/46] hw/arm/raspi: Trivial code movement Peter Maydell
2020-02-13 14:41 ` [PULL 39/46] hw/arm/raspi: Make machines children of abstract RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 40/46] hw/arm/raspi: Make board_rev a field of RaspiMachineClass Peter Maydell
2020-02-13 14:41 ` [PULL 41/46] hw/arm/raspi: Let class_init() directly call raspi_machine_init() Peter Maydell
2020-02-13 14:41 ` [PULL 42/46] hw/arm/raspi: Set default RAM size to size encoded in board revision Peter Maydell
2020-02-13 14:41 ` [PULL 43/46] hw/arm/raspi: Extract the board model from the " Peter Maydell
2020-02-13 14:41 ` [PULL 44/46] hw/arm/raspi: Use a unique raspi_machine_class_init() method Peter Maydell
2020-02-13 14:41 ` [PULL 45/46] hw/arm/raspi: Extract the cores count from the board revision Peter Maydell
2020-02-13 14:41 ` [PULL 46/46] target/arm: Implement ARMv8.1-VMID16 extension Peter Maydell
2020-02-14 16:43 ` [PULL 00/46] target-arm queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200213144145.818-29-peter.maydell@linaro.org \
    --to=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).