From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: "Eric Auger" <eric.auger@redhat.com>,
"Aaron Lindsay" <aaron@os.amperecomputing.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>
Subject: [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields
Date: Fri, 14 Feb 2020 17:51:15 +0000 [thread overview]
Message-ID: <20200214175116.9164-21-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200214175116.9164-1-peter.maydell@linaro.org>
Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from
some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes
no difference in behaviour, it's just more consistent.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 276030a5cf3..c6af3290caf 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3453,18 +3453,18 @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id)
{
/* Return true if D16-D31 are implemented */
- return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >= 2;
+ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >= 2;
}
static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
+ return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point */
- return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
+ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0;
}
/*
@@ -3474,32 +3474,32 @@ static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
*/
static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0;
}
static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1;
}
static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 1;
}
static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 2;
}
static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 3;
}
static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
{
- return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
+ return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
}
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
--
2.20.1
next prev parent reply other threads:[~2020-02-14 18:05 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 17:50 [PATCH v2 00/21] arm: ARMv8.1- and v8.4-PMU, ID reg cleanup, [H]ACTLR2 Peter Maydell
2020-02-14 17:50 ` [PATCH v2 01/21] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Peter Maydell
2020-02-14 17:50 ` [PATCH v2 02/21] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Peter Maydell
2020-02-14 20:10 ` Richard Henderson
2020-02-14 17:50 ` [PATCH v2 03/21] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Peter Maydell
2020-02-14 17:50 ` [PATCH v2 04/21] target/arm: Define and use any_predinv isar_feature test Peter Maydell
2020-02-14 17:51 ` [PATCH v2 05/21] target/arm: Factor out PMU register definitions Peter Maydell
2020-02-14 17:51 ` [PATCH v2 06/21] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Peter Maydell
2020-02-14 17:51 ` [PATCH v2 07/21] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Peter Maydell
2020-02-14 17:51 ` [PATCH v2 08/21] target/arm: Define an aa32_pmu_8_1 isar feature test function Peter Maydell
2020-02-14 17:51 ` [PATCH v2 09/21] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Peter Maydell
2020-02-14 17:51 ` [PATCH v2 10/21] target/arm: Stop assuming DBGDIDR always exists Peter Maydell
2020-02-14 20:15 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 11/21] target/arm: Move DBGDIDR into ARMISARegisters Peter Maydell
2020-02-14 20:16 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 12/21] target/arm: Read debug-related ID registers from KVM Peter Maydell
2020-02-14 20:27 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 13/21] target/arm: Implement ARMv8.1-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 14/21] target/arm: Implement ARMv8.4-PMU extension Peter Maydell
2020-02-14 17:51 ` [PATCH v2 15/21] target/arm: Provide ARMv8.4-PMU in '-cpu max' Peter Maydell
2020-02-14 17:51 ` [PATCH v2 16/21] target/arm: Correct definition of PMCRDP Peter Maydell
2020-02-14 17:51 ` [PATCH v2 17/21] target/arm: Correct handling of PMCR_EL0.LC bit Peter Maydell
2020-02-14 17:51 ` [PATCH v2 18/21] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Peter Maydell
2020-02-14 20:30 ` Richard Henderson
2020-02-14 17:51 ` [PATCH v2 19/21] target/arm: Use isar_feature function for testing AA32HPD feature Peter Maydell
2020-02-14 20:32 ` Richard Henderson
2020-02-14 17:51 ` Peter Maydell [this message]
2020-02-14 20:32 ` [PATCH v2 20/21] target/arm: Use FIELD_EX32 for testing 32-bit fields Richard Henderson
2020-02-14 17:51 ` [PATCH v2 21/21] target/arm: Correctly implement ACTLR2, HACTLR2 Peter Maydell
2020-02-14 20:42 ` Richard Henderson
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