From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT
Date: Fri, 14 Feb 2020 11:46:40 -0800 [thread overview]
Message-ID: <20200214194643.23317-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200214194643.23317-1-richard.henderson@linaro.org>
Writes to AdvSIMD registers flush the bits above 128.
Buglink: https://bugs.launchpad.net/bugs/1863247
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7c26c3bfeb..620a429067 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6895,6 +6895,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_resh);
+ clear_vec_high(s, true, rd);
}
/* TBL/TBX
--
2.20.1
next prev parent reply other threads:[~2020-02-14 19:49 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
2020-02-14 19:46 ` Richard Henderson [this message]
2020-02-14 19:46 ` [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Richard Henderson
2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
2020-02-14 19:46 ` [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS Richard Henderson
2020-02-18 17:28 ` [PATCH 0/4] target/arm: fix some simd writes vs sve Peter Maydell
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