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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org
Subject: [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS
Date: Fri, 14 Feb 2020 11:46:43 -0800
Message-ID: <20200214194643.23317-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200214194643.23317-1-richard.henderson@linaro.org>

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b83d09dbcd..bd68588a71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
     write_vec_element(s, tmp, rd, dst_index, size);
 
     tcg_temp_free_i64(tmp);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 
@@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
 
     idx = extract32(imm5, 1 + size, 4 - size);
     write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 /*
-- 
2.20.1



  parent reply index

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
2020-02-14 19:46 ` [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Richard Henderson
2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
2020-02-14 19:46 ` Richard Henderson [this message]
2020-02-18 17:28 ` [PATCH 0/4] target/arm: fix some simd writes vs sve Peter Maydell

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