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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 13/33] target/arm: Add missing checks for fpsp_v2
Date: Fri, 28 Feb 2020 16:38:20 +0000	[thread overview]
Message-ID: <20200228163840.23585-14-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

We will eventually remove the early ARM_FEATURE_VFP test,
so add a proper test for each trans_* that does not already
have another ISA test.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++----
 1 file changed, 69 insertions(+), 9 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 51d46f43027..f88a95438fc 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
     int pass;
     uint32_t offset;
 
+    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
+    if (a->size == 2
+        ? !dc_isar_feature(aa32_fpsp_v2, s)
+        : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
     /* UNDEF accesses to D16-D31 if they don't exist */
     if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
         return false;
@@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
     pass = extract32(offset, 2, 1);
     offset = extract32(offset, 0, 2) * 8;
 
-    if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
-        return false;
-    }
-
     if (!vfp_access_check(s)) {
         return true;
     }
@@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
     int pass;
     uint32_t offset;
 
+    /* SIZE == 2 is a VFP instruction; otherwise NEON.  */
+    if (a->size == 2
+        ? !dc_isar_feature(aa32_fpsp_v2, s)
+        : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+        return false;
+    }
+
     /* UNDEF accesses to D16-D31 if they don't exist */
     if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) {
         return false;
@@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
     pass = extract32(offset, 2, 1);
     offset = extract32(offset, 0, 2) * 8;
 
-    if (a->size != 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) {
-        return false;
-    }
-
     if (!vfp_access_check(s)) {
         return true;
     }
@@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
     TCGv_i32 tmp;
     bool ignore_vfp_enabled = false;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (arm_dc_feature(s, ARM_FEATURE_M)) {
         /*
          * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
@@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMOV_single *a)
 {
     TCGv_i32 tmp;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!vfp_access_check(s)) {
         return true;
     }
@@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV_64_sp *a)
 {
     TCGv_i32 tmp;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     /*
      * VMOV between two general-purpose registers and two single precision
      * floating point registers
@@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_64_dp *a)
 
     /*
      * VMOV between two general-purpose registers and one double precision
-     * floating point register
+     * floating point register.  Note that this does not require support
+     * for double precision arithmetic.
      */
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
 
     /* UNDEF accesses to D16-D31 if they don't exist */
     if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
@@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
     uint32_t offset;
     TCGv_i32 addr, tmp;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!vfp_access_check(s)) {
         return true;
     }
@@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
     TCGv_i32 addr;
     TCGv_i64 tmp;
 
+    /* Note that this does not require support for double arithmetic.  */
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     /* UNDEF accesses to D16-D31 if they don't exist */
     if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
         return false;
@@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
     TCGv_i32 addr, tmp;
     int i, n;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     n = a->imm;
 
     if (n == 0 || (a->vd + n) > 32) {
@@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
     TCGv_i64 tmp;
     int i, n;
 
+    /* Note that this does not require support for double arithmetic.  */
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     n = a->imm >> 1;
 
     if (n == 0 || (a->vd + n) > 32 || n > 16) {
@@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3OpSPFn *fn,
     TCGv_i32 f0, f1, fd;
     TCGv_ptr fpst;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!dc_isar_feature(aa32_fpshvec, s) &&
         (veclen != 0 || s->vec_stride != 0)) {
         return false;
@@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
     int veclen = s->vec_len;
     TCGv_i32 f0, fd;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!dc_isar_feature(aa32_fpshvec, s) &&
         (veclen != 0 || s->vec_stride != 0)) {
         return false;
@@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_sp *a)
 {
     TCGv_i32 vd, vm;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     /* Vm/M bits must be zero for the Z variant */
     if (a->z && a->vm != 0) {
         return false;
@@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_VCVT_int_sp *a)
     TCGv_i32 vm;
     TCGv_ptr fpst;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!vfp_access_check(s)) {
         return true;
     }
@@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_VCVT_sp_int *a)
     TCGv_i32 vm;
     TCGv_ptr fpst;
 
+    if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+        return false;
+    }
+
     if (!vfp_access_check(s)) {
         return true;
     }
-- 
2.20.1



  parent reply	other threads:[~2020-02-28 16:45 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
2020-02-28 16:38 ` [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Peter Maydell
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
2020-02-28 16:38 ` Peter Maydell [this message]
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
2020-02-28 16:38 ` [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Peter Maydell
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
2020-02-28 16:38 ` [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Peter Maydell
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
2021-05-19 17:50   ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
2020-10-17 17:51   ` Philippe Mathieu-Daudé
2020-10-19  6:31     ` Thomas Huth
2020-10-19  9:30       ` Philippe Mathieu-Daudé
2020-10-19  9:43         ` Philippe Mathieu-Daudé
2020-10-23 15:43           ` Igor Mammedov
2020-10-23 17:39             ` Philippe Mathieu-Daudé
2020-10-23 19:04               ` Igor Mammedov
2020-10-25 17:03                 ` Peter Maydell
2020-10-26 13:36                   ` Igor Mammedov
2020-10-26 14:26                     ` Peter Maydell
2020-10-27 10:54                       ` Igor Mammedov
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell

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