From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns
Date: Fri, 28 Feb 2020 16:38:27 +0000 [thread overview]
Message-ID: <20200228163840.23585-21-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
Those vfp instructions without extra opcode fields can
share a common @format for brevity.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224222232.13807-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/vfp.decode | 134 ++++++++++++++++--------------------------
1 file changed, 52 insertions(+), 82 deletions(-)
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 592fe9e1e42..4f294f88be5 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -46,6 +46,14 @@
%vmov_imm 16:4 0:4
+@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
+@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
+@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
+@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
+@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
+
# VMOV scalar to general-purpose register; note that this does
# include some Neon cases.
VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
@@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
vn=%vn_dp
VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
-VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
- vn=%vn_sp
+VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
-VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
- vm=%vm_sp
-VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
- vm=%vm_dp
+VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
+VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
# Note that the half-precision variants of VLDR and VSTR are
# not part of this decodetree at all because they have bits [9:8] == 0b01
-VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
- vd=%vd_sp
-VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
- vd=%vd_dp
+VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
+VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
# We split the load/store multiple up into two patterns to avoid
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
@@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
vd=%vd_dp p=1 u=0 w=1
# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
-VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
-VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
+VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
-VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
+VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
-VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
+VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
-VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
+VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
-VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
+VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
-VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
+VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
-VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \
- vm=%vm_sp vn=%vn_sp vd=%vd_sp
-VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \
- vm=%vm_dp vn=%vn_dp vd=%vd_dp
+VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
+VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
@@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
vd=%vd_dp imm=%vmov_imm
-VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
+VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
-VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
+VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
-VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
+VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
-VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
+VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
@@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
-# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit
+# VCVTB and VCVTT to f16: Vd format is always vd_sp;
+# Vm format depends on size bit
VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
vd=%vd_sp vm=%vm_sp
VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
vd=%vd_sp vm=%vm_dp
-VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
+VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
-VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
+VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
-VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \
- vd=%vd_sp vm=%vm_sp
-VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \
- vd=%vd_dp vm=%vm_dp
+VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
+VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
-# VCVT between single and double: Vm precision depends on size; Vd is its reverse
-VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \
- vd=%vd_dp vm=%vm_sp
-VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+# VCVT between single and double:
+# Vm precision depends on size; Vd is its reverse
+VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
+VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
# VCVT from integer to floating point: Vm always single; Vd depends on size
VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
@@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
vd=%vd_dp vm=%vm_sp
# VJCVT is always dp to sp
-VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \
- vd=%vd_sp vm=%vm_dp
+VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
# VCVT between floating-point and fixed-point. The immediate value
# is in the same format as a Vm single-precision register number.
--
2.20.1
next prev parent reply other threads:[~2020-02-28 17:02 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:38 [PULL 00/33] target-arm queue Peter Maydell
2020-02-28 16:38 ` [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Peter Maydell
2020-02-28 16:38 ` [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Peter Maydell
2020-02-28 16:38 ` [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Peter Maydell
2020-02-28 16:38 ` [PULL 04/33] arm_gic: Mask the un-supported priority bits Peter Maydell
2020-02-28 16:38 ` [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Peter Maydell
2020-02-28 16:38 ` [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Peter Maydell
2020-02-28 16:38 ` [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Peter Maydell
2020-02-28 16:38 ` [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Peter Maydell
2020-02-28 16:38 ` [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Peter Maydell
2020-02-28 16:38 ` [PULL 11/33] target/arm: Perform fpdp_v2 check first Peter Maydell
2020-02-28 16:38 ` [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Peter Maydell
2020-02-28 16:38 ` [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Peter Maydell
2020-02-28 16:38 ` [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Peter Maydell
2020-02-28 16:38 ` [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Peter Maydell
2020-02-28 16:38 ` [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Peter Maydell
2020-02-28 16:38 ` [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Peter Maydell
2020-02-28 16:38 ` [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Peter Maydell
2020-02-28 16:38 ` [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Peter Maydell
2020-02-28 16:38 ` Peter Maydell [this message]
2020-02-28 16:38 ` [PULL 21/33] target/arm: Split VFM decode Peter Maydell
2020-02-28 16:38 ` [PULL 22/33] target/arm: Split VMINMAXNM decode Peter Maydell
2020-02-28 16:38 ` [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Peter Maydell
2021-05-19 17:50 ` Philippe Mathieu-Daudé
2020-02-28 16:38 ` [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Peter Maydell
2020-02-28 16:38 ` [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Peter Maydell
2020-10-17 17:51 ` Philippe Mathieu-Daudé
2020-10-19 6:31 ` Thomas Huth
2020-10-19 9:30 ` Philippe Mathieu-Daudé
2020-10-19 9:43 ` Philippe Mathieu-Daudé
2020-10-23 15:43 ` Igor Mammedov
2020-10-23 17:39 ` Philippe Mathieu-Daudé
2020-10-23 19:04 ` Igor Mammedov
2020-10-25 17:03 ` Peter Maydell
2020-10-26 13:36 ` Igor Mammedov
2020-10-26 14:26 ` Peter Maydell
2020-10-27 10:54 ` Igor Mammedov
2020-02-28 16:38 ` [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Peter Maydell
2020-02-28 16:38 ` [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Peter Maydell
2020-02-28 16:38 ` [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Peter Maydell
2020-02-28 16:38 ` [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Peter Maydell
2020-02-28 16:38 ` [PULL 30/33] target/arm: Implement v8.3-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 31/33] target/arm: Implement v8.4-RCPC Peter Maydell
2020-02-28 16:38 ` [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Peter Maydell
2020-02-28 16:38 ` [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Peter Maydell
2020-02-28 17:59 ` [PULL 00/33] target-arm queue Peter Maydell
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