From: Havard Skinnemoen <hskinnemoen@google.com>
To: peter.maydell@linaro.org, f4bug@amsat.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
Avi.Fishman@nuvoton.com, kfting@nuvoton.com,
"Havard Skinnemoen" <hskinnemoen@google.com>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v5 08/11] hw/mem: Stubbed out NPCM7xx Memory Controller model
Date: Wed, 8 Jul 2020 17:36:05 -0700 [thread overview]
Message-ID: <20200709003608.3834629-9-hskinnemoen@google.com> (raw)
In-Reply-To: <20200709003608.3834629-1-hskinnemoen@google.com>
This just implements the bare minimum to cause the boot block to skip
memory initialization.
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
---
include/hw/arm/npcm7xx.h | 2 +
include/hw/mem/npcm7xx_mc.h | 36 ++++++++++++++++
hw/arm/npcm7xx.c | 6 +++
hw/mem/npcm7xx_mc.c | 84 +++++++++++++++++++++++++++++++++++++
hw/mem/Makefile.objs | 1 +
5 files changed, 129 insertions(+)
create mode 100644 include/hw/mem/npcm7xx_mc.h
create mode 100644 hw/mem/npcm7xx_mc.c
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index 0fd4ae4133..3ae9e5dca2 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -18,6 +18,7 @@
#include "hw/boards.h"
#include "hw/cpu/a9mpcore.h"
+#include "hw/mem/npcm7xx_mc.h"
#include "hw/misc/npcm7xx_clk.h"
#include "hw/misc/npcm7xx_gcr.h"
#include "hw/nvram/npcm7xx_otp.h"
@@ -71,6 +72,7 @@ typedef struct NPCM7xxState {
NPCM7xxTimerCtrlState tim[3];
NPCM7xxOTPState key_storage;
NPCM7xxOTPState fuse_array;
+ NPCM7xxMCState mc;
} NPCM7xxState;
#define TYPE_NPCM7XX "npcm7xx"
diff --git a/include/hw/mem/npcm7xx_mc.h b/include/hw/mem/npcm7xx_mc.h
new file mode 100644
index 0000000000..7ed38be243
--- /dev/null
+++ b/include/hw/mem/npcm7xx_mc.h
@@ -0,0 +1,36 @@
+/*
+ * Nuvoton NPCM7xx Memory Controller stub
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+#ifndef NPCM7XX_MC_H
+#define NPCM7XX_MC_H
+
+#include "exec/memory.h"
+#include "hw/sysbus.h"
+
+/**
+ * struct NPCM7xxMCState - Device state for the memory controller.
+ * @parent: System bus device.
+ * @mmio: Memory region through which registers are accessed.
+ */
+typedef struct NPCM7xxMCState {
+ SysBusDevice parent;
+
+ MemoryRegion mmio;
+} NPCM7xxMCState;
+
+#define TYPE_NPCM7XX_MC "npcm7xx-mc"
+#define NPCM7XX_MC(obj) OBJECT_CHECK(NPCM7xxMCState, (obj), TYPE_NPCM7XX_MC)
+
+#endif /* NPCM7XX_MC_H */
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index 70eaa2347f..4d227bb74b 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -42,6 +42,7 @@
#define NPCM7XX_CPUP_BA (0xf03fe000)
#define NPCM7XX_GCR_BA (0xf0800000)
#define NPCM7XX_CLK_BA (0xf0801000)
+#define NPCM7XX_MC_BA (0xf0824000)
/* Internal AHB SRAM */
#define NPCM7XX_RAM3_BA (0xc0008000)
@@ -165,6 +166,7 @@ static void npcm7xx_init(Object *obj)
TYPE_NPCM7XX_KEY_STORAGE);
object_initialize_child(obj, "otp2", &s->fuse_array,
TYPE_NPCM7XX_FUSE_ARRAY);
+ object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
@@ -230,6 +232,10 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
npcm7xx_init_fuses(s);
+ /* Fake Memory Controller (MC) */
+ sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
+
/* Timer Modules (TIM) */
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
new file mode 100644
index 0000000000..0435d06ab4
--- /dev/null
+++ b/hw/mem/npcm7xx_mc.c
@@ -0,0 +1,84 @@
+/*
+ * Nuvoton NPCM7xx Memory Controller stub
+ *
+ * Copyright 2020 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "qemu/osdep.h"
+
+#include "hw/mem/npcm7xx_mc.h"
+#include "qapi/error.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+
+#define NPCM7XX_MC_REGS_SIZE (4 * KiB)
+
+static uint64_t npcm7xx_mc_read(void *opaque, hwaddr addr, unsigned int size)
+{
+ /*
+ * If bits 8..11 @ offset 0 are not zero, the boot block thinks the memory
+ * controller has already been initialized and will skip DDR training.
+ */
+ if (addr == 0) {
+ return 0x100;
+ }
+
+ qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
+
+ return 0;
+}
+
+static void npcm7xx_mc_write(void *opaque, hwaddr addr, uint64_t v,
+ unsigned int size)
+{
+ qemu_log_mask(LOG_UNIMP, "%s: mostly unimplemented\n", __func__);
+}
+
+static const MemoryRegionOps npcm7xx_mc_ops = {
+ .read = npcm7xx_mc_read,
+ .write = npcm7xx_mc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
+{
+ NPCM7xxMCState *s = NPCM7XX_MC(dev);
+
+ memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
+ NPCM7XX_MC_REGS_SIZE);
+ sysbus_init_mmio(&s->parent, &s->mmio);
+}
+
+static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "NPCM7xx Memory Controller stub";
+ dc->realize = npcm7xx_mc_realize;
+}
+
+static const TypeInfo npcm7xx_mc_types[] = {
+ {
+ .name = TYPE_NPCM7XX_MC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(NPCM7xxMCState),
+ .class_init = npcm7xx_mc_class_init,
+ },
+};
+DEFINE_TYPES(npcm7xx_mc_types);
diff --git a/hw/mem/Makefile.objs b/hw/mem/Makefile.objs
index 56345befd0..9a33ef7b35 100644
--- a/hw/mem/Makefile.objs
+++ b/hw/mem/Makefile.objs
@@ -1,3 +1,4 @@
common-obj-$(CONFIG_DIMM) += pc-dimm.o
common-obj-y += memory-device.o
+common-obj-$(CONFIG_NPCM7XX) += npcm7xx_mc.o
common-obj-$(CONFIG_NVDIMM) += nvdimm.o
--
2.27.0.383.g050319c2ae-goog
next prev parent reply other threads:[~2020-07-09 0:44 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-09 0:35 [PATCH v5 00/11] Add Nuvoton NPCM730/NPCM750 SoCs and two BMC machines Havard Skinnemoen
2020-07-09 0:35 ` [PATCH v5 01/11] hw/misc: Add NPCM7xx System Global Control Registers device model Havard Skinnemoen
2020-07-09 6:04 ` Philippe Mathieu-Daudé
2020-07-09 6:43 ` Havard Skinnemoen
2020-07-09 16:23 ` Philippe Mathieu-Daudé
2020-07-09 17:09 ` Havard Skinnemoen
2020-07-09 17:24 ` Philippe Mathieu-Daudé
2020-07-09 17:42 ` Havard Skinnemoen
2020-07-10 9:31 ` Philippe Mathieu-Daudé
2020-07-11 6:46 ` Havard Skinnemoen
2020-07-12 5:49 ` Havard Skinnemoen
2020-07-09 0:35 ` [PATCH v5 02/11] hw/misc: Add NPCM7xx Clock Controller " Havard Skinnemoen
2020-07-15 7:18 ` Philippe Mathieu-Daudé
2020-07-09 0:36 ` [PATCH v5 03/11] hw/timer: Add NPCM7xx Timer " Havard Skinnemoen
2020-07-15 7:25 ` Philippe Mathieu-Daudé
2020-07-15 23:04 ` Havard Skinnemoen
2020-07-16 8:04 ` Philippe Mathieu-Daudé
2020-07-09 0:36 ` [PATCH v5 04/11] hw/arm: Add NPCM730 and NPCM750 SoC models Havard Skinnemoen
2020-07-09 6:11 ` Philippe Mathieu-Daudé
2020-07-13 15:02 ` Cédric Le Goater
2020-07-14 0:44 ` Havard Skinnemoen
2020-07-14 11:37 ` Philippe Mathieu-Daudé
2020-07-14 16:01 ` Markus Armbruster
2020-07-14 17:11 ` Philippe Mathieu-Daudé
2020-07-15 1:03 ` Havard Skinnemoen
2020-07-15 9:35 ` Markus Armbruster
2020-07-09 0:36 ` [PATCH v5 05/11] hw/arm: Add two NPCM7xx-based machines Havard Skinnemoen
2020-07-09 5:57 ` Philippe Mathieu-Daudé
2020-07-09 6:09 ` Philippe Mathieu-Daudé
2020-07-09 0:36 ` [PATCH v5 06/11] hw/arm: Load -bios image as a boot ROM for npcm7xx Havard Skinnemoen
2020-07-13 17:50 ` Philippe Mathieu-Daudé
2020-07-09 0:36 ` [PATCH v5 07/11] hw/nvram: NPCM7xx OTP device model Havard Skinnemoen
2020-07-09 0:36 ` Havard Skinnemoen [this message]
2020-07-09 16:29 ` [PATCH v5 08/11] hw/mem: Stubbed out NPCM7xx Memory Controller model Philippe Mathieu-Daudé
2020-07-09 0:36 ` [PATCH v5 09/11] hw/ssi: NPCM7xx Flash Interface Unit device model Havard Skinnemoen
2020-07-09 17:00 ` Philippe Mathieu-Daudé
2020-07-12 5:42 ` Havard Skinnemoen
2020-07-13 17:38 ` Philippe Mathieu-Daudé
2020-07-14 2:39 ` Havard Skinnemoen
2020-07-09 0:36 ` [PATCH v5 10/11] hw/arm: Wire up BMC boot flash for npcm750-evb and quanta-gsj Havard Skinnemoen
2020-07-13 14:57 ` Cédric Le Goater
2020-07-13 17:59 ` Philippe Mathieu-Daudé
2020-07-13 18:02 ` Philippe Mathieu-Daudé
2020-07-14 2:56 ` Havard Skinnemoen
2020-07-14 9:16 ` Markus Armbruster
2020-07-14 11:29 ` Philippe Mathieu-Daudé
2020-07-14 16:21 ` Markus Armbruster
2020-07-14 17:16 ` Philippe Mathieu-Daudé
2020-07-15 9:00 ` Markus Armbruster
2020-07-15 10:57 ` Philippe Mathieu-Daudé
2020-07-15 20:54 ` Havard Skinnemoen
2020-07-16 20:56 ` Havard Skinnemoen
2020-07-17 7:48 ` Philippe Mathieu-Daudé
2020-07-17 8:03 ` Thomas Huth
2020-07-17 8:27 ` Philippe Mathieu-Daudé
2020-07-17 9:00 ` Philippe Mathieu-Daudé
2020-07-17 19:18 ` Havard Skinnemoen
2020-07-17 20:21 ` Cédric Le Goater
2020-07-17 20:52 ` Philippe Mathieu-Daudé
2020-07-17 20:57 ` Havard Skinnemoen
2020-07-20 7:58 ` Markus Armbruster
2020-07-15 7:42 ` Cédric Le Goater
2020-07-15 21:19 ` Havard Skinnemoen
2020-07-09 0:36 ` [PATCH v5 11/11] docs/system: Add Nuvoton machine documentation Havard Skinnemoen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200709003608.3834629-9-hskinnemoen@google.com \
--to=hskinnemoen@google.com \
--cc=Avi.Fishman@nuvoton.com \
--cc=clg@kaod.org \
--cc=f4bug@amsat.org \
--cc=kfting@nuvoton.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).