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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 16/22] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode
Date: Mon, 24 Aug 2020 15:29:28 +0100	[thread overview]
Message-ID: <20200824142934.20850-17-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200824142934.20850-1-peter.maydell@linaro.org>

Implement the fp16 versions of the VFP VCVT instruction forms
which convert between floating point and integer with a specified
rounding mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/vfp-uncond.decode   |  6 ++++--
 target/arm/translate-vfp.c.inc | 32 ++++++++++++++++++++++++--------
 2 files changed, 28 insertions(+), 10 deletions(-)

diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode
index ee700e51972..b7cd9d11ed5 100644
--- a/target/arm/vfp-uncond.decode
+++ b/target/arm/vfp-uncond.decode
@@ -64,7 +64,9 @@ VRINT       1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \
             vm=%vm_dp vd=%vd_dp dp=1
 
 # VCVT float to int with specified rounding mode; Vd is always single-precision
+VCVT        1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \
+            vm=%vm_sp vd=%vd_sp sz=1
 VCVT        1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
-            vm=%vm_sp vd=%vd_sp dp=0
+            vm=%vm_sp vd=%vd_sp sz=2
 VCVT        1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
-            vm=%vm_dp vd=%vd_sp dp=1
+            vm=%vm_dp vd=%vd_sp sz=3
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index fdf486b7c15..583e7ccdb20 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -396,7 +396,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
 static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
 {
     uint32_t rd, rm;
-    bool dp = a->dp;
+    int sz = a->sz;
     TCGv_ptr fpst;
     TCGv_i32 tcg_rmode, tcg_shift;
     int rounding = fp_decode_rm[a->rm];
@@ -406,12 +406,16 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         return false;
     }
 
-    if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) {
+    if (sz == 3 && !dc_isar_feature(aa32_fpdp_v2, s)) {
+        return false;
+    }
+
+    if (sz == 1 && !dc_isar_feature(aa32_fp16_arith, s)) {
         return false;
     }
 
     /* UNDEF accesses to D16-D31 if they don't exist */
-    if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
+    if (sz == 3 && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) {
         return false;
     }
 
@@ -422,14 +426,18 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         return true;
     }
 
-    fpst = fpstatus_ptr(FPST_FPCR);
+    if (sz == 1) {
+        fpst = fpstatus_ptr(FPST_FPCR_F16);
+    } else {
+        fpst = fpstatus_ptr(FPST_FPCR);
+    }
 
     tcg_shift = tcg_const_i32(0);
 
     tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rounding));
     gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
 
-    if (dp) {
+    if (sz == 3) {
         TCGv_i64 tcg_double, tcg_res;
         TCGv_i32 tcg_tmp;
         tcg_double = tcg_temp_new_i64();
@@ -451,10 +459,18 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
         tcg_single = tcg_temp_new_i32();
         tcg_res = tcg_temp_new_i32();
         neon_load_reg32(tcg_single, rm);
-        if (is_signed) {
-            gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
+        if (sz == 1) {
+            if (is_signed) {
+                gen_helper_vfp_toslh(tcg_res, tcg_single, tcg_shift, fpst);
+            } else {
+                gen_helper_vfp_toulh(tcg_res, tcg_single, tcg_shift, fpst);
+            }
         } else {
-            gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
+            if (is_signed) {
+                gen_helper_vfp_tosls(tcg_res, tcg_single, tcg_shift, fpst);
+            } else {
+                gen_helper_vfp_touls(tcg_res, tcg_single, tcg_shift, fpst);
+            }
         }
         neon_store_reg32(tcg_res, rd);
         tcg_temp_free_i32(tcg_res);
-- 
2.20.1



  parent reply	other threads:[~2020-08-24 14:36 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-24 14:29 [PATCH 00/22] target/arm: Implement fp16 for AArch32 VFP Peter Maydell
2020-08-24 14:29 ` [PATCH 01/22] target/arm: Remove local definitions of float constants Peter Maydell
2020-08-25 18:04   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 02/22] target/arm: Use correct ID register check for aa32_fp16_arith Peter Maydell
2020-08-25 18:06   ` Richard Henderson
2020-08-27 13:46     ` Peter Maydell
2020-08-24 14:29 ` [PATCH 03/22] target/arm: Implement VFP fp16 for VFP_BINOP operations Peter Maydell
2020-08-25 18:14   ` Richard Henderson
2020-08-27 13:39     ` Peter Maydell
2020-08-24 14:29 ` [PATCH 04/22] target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL Peter Maydell
2020-08-25 18:18   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 05/22] target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS Peter Maydell
2020-08-25 18:19   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 06/22] target/arm: Implement VFP fp16 for fused-multiply-add Peter Maydell
2020-08-25 18:21   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 07/22] target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp() Peter Maydell
2020-08-25 18:22   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 08/22] target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT Peter Maydell
2020-08-25 18:24   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 09/22] target/arm: Implement VFP fp16 for VMOV immediate Peter Maydell
2020-08-25 18:25   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 10/22] target/arm: Implement VFP fp16 VCMP Peter Maydell
2020-08-25 18:39   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 11/22] target/arm: Implement VFP fp16 VLDR and VSTR Peter Maydell
2020-08-25 18:44   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 12/22] target/arm: Implement VFP fp16 VCVT between float and integer Peter Maydell
2020-08-25 18:45   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 13/22] target/arm: Make VFP_CONV_FIX macros take separate float type and float size Peter Maydell
2020-08-25 18:47   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 14/22] target/arm: Use macros instead of open-coding fp16 conversion helpers Peter Maydell
2020-08-25 18:48   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 15/22] target/arm: Implement VFP fp16 VCVT between float and fixed-point Peter Maydell
2020-08-25 18:49   ` Richard Henderson
2020-08-24 14:29 ` Peter Maydell [this message]
2020-08-25 18:51   ` [PATCH 16/22] target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode Richard Henderson
2020-08-24 14:29 ` [PATCH 17/22] target/arm: Implement VFP fp16 VSEL Peter Maydell
2020-08-25 19:19   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 18/22] target/arm: Implement VFP fp16 VRINT* Peter Maydell
2020-08-25 19:21   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 19/22] target/arm: Implement new VFP fp16 insn VINS Peter Maydell
2020-08-25 19:23   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 20/22] target/arm: Implement new VFP fp16 insn VMOVX Peter Maydell
2020-08-25 19:25   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 21/22] target/arm: Implement VFP fp16 VMOV between gp and halfprec registers Peter Maydell
2020-08-25 19:29   ` Richard Henderson
2020-08-24 14:29 ` [PATCH 22/22] target/arm: Enable FP16 in '-cpu max' Peter Maydell
2020-08-25 19:30   ` Richard Henderson

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