From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Damien Hedde" <damien.hedde@greensocs.com>,
"Huacai Chen" <zltjiangshi@gmail.com>,
"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
"Eduardo Habkost" <ehabkost@redhat.com>,
"Paul Burton" <paulburton@kernel.org>,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Hervé Poussineau" <hpoussin@reactos.org>,
"Cleber Rosa" <crosa@redhat.com>,
"Huacai Chen" <chenhc@lemote.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Aurelien Jarno" <aurelien@aurel32.net>,
"Richard Henderson" <rth@twiddle.net>
Subject: [PATCH 02/16] target/mips: Move cpu_mips_get_random() with CP0 helpers
Date: Mon, 28 Sep 2020 19:15:25 +0200 [thread overview]
Message-ID: <20200928171539.788309-3-f4bug@amsat.org> (raw)
In-Reply-To: <20200928171539.788309-1-f4bug@amsat.org>
The get_random() helper uses the CP0_Wired register, which is
unrelated to the CP0_Count register use as timer.
Commit e16fe40c872 ("Move the MIPS CPU timer in a separate file")
incorrectly moved this get_random() helper with timer specific
code. Move it back to generic CP0 helpers.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/internal.h | 2 +-
target/mips/cp0_helper.c | 25 +++++++++++++++++++++++++
target/mips/cp0_timer.c | 25 -------------------------
3 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 7f159a9230c..087cabaa6d4 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -144,6 +144,7 @@ void r4k_helper_tlbr(CPUMIPSState *env);
void r4k_helper_tlbinv(CPUMIPSState *env);
void r4k_helper_tlbinvf(CPUMIPSState *env);
void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra);
+uint32_t cpu_mips_get_random(CPUMIPSState *env);
void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,
@@ -209,7 +210,6 @@ void cpu_state_reset(CPUMIPSState *s);
void cpu_mips_realize_env(CPUMIPSState *env);
/* cp0_timer.c */
-uint32_t cpu_mips_get_random(CPUMIPSState *env);
uint32_t cpu_mips_get_count(CPUMIPSState *env);
void cpu_mips_store_count(CPUMIPSState *env, uint32_t value);
void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c
index de64add038b..12143ac55b9 100644
--- a/target/mips/cp0_helper.c
+++ b/target/mips/cp0_helper.c
@@ -203,6 +203,31 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
*tcst |= asid;
}
+/* XXX: do not use a global */
+uint32_t cpu_mips_get_random(CPUMIPSState *env)
+{
+ static uint32_t seed = 1;
+ static uint32_t prev_idx;
+ uint32_t idx;
+ uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
+
+ if (nb_rand_tlb == 1) {
+ return env->tlb->nb_tlb - 1;
+ }
+
+ /* Don't return same value twice, so get another value */
+ do {
+ /*
+ * Use a simple algorithm of Linear Congruential Generator
+ * from ISO/IEC 9899 standard.
+ */
+ seed = 1103515245 * seed + 12345;
+ idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
+ } while (idx == prev_idx);
+ prev_idx = idx;
+ return idx;
+}
+
/* CP0 helpers */
target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
{
diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c
index bd7efb152dd..9c38e9da1c8 100644
--- a/target/mips/cp0_timer.c
+++ b/target/mips/cp0_timer.c
@@ -29,31 +29,6 @@
#define TIMER_PERIOD 10 /* 10 ns period for 100 Mhz frequency */
-/* XXX: do not use a global */
-uint32_t cpu_mips_get_random(CPUMIPSState *env)
-{
- static uint32_t seed = 1;
- static uint32_t prev_idx = 0;
- uint32_t idx;
- uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired;
-
- if (nb_rand_tlb == 1) {
- return env->tlb->nb_tlb - 1;
- }
-
- /* Don't return same value twice, so get another value */
- do {
- /*
- * Use a simple algorithm of Linear Congruential Generator
- * from ISO/IEC 9899 standard.
- */
- seed = 1103515245 * seed + 12345;
- idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired;
- } while (idx == prev_idx);
- prev_idx = idx;
- return idx;
-}
-
/* MIPS R4K timer */
static void cpu_mips_timer_update(CPUMIPSState *env)
{
--
2.26.2
next prev parent reply other threads:[~2020-09-28 17:17 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-28 17:15 [PATCH 00/16] hw/mips: Set CPU frequency Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 01/16] hw/core/cpu: Let CPU object have a clock source Philippe Mathieu-Daudé
2020-09-30 7:43 ` Igor Mammedov
2020-09-30 10:16 ` Philippe Mathieu-Daudé
2020-10-05 16:40 ` Igor Mammedov
2020-10-05 17:19 ` Philippe Mathieu-Daudé
2020-10-05 17:44 ` Eduardo Habkost
2020-10-05 18:09 ` Philippe Mathieu-Daudé
2020-10-05 18:29 ` Philippe Mathieu-Daudé
2020-10-05 19:22 ` Eduardo Habkost
2020-10-06 18:11 ` Philippe Mathieu-Daudé
2020-10-06 19:53 ` Philippe Mathieu-Daudé
2020-10-05 18:43 ` Eduardo Habkost
2020-09-28 17:15 ` Philippe Mathieu-Daudé [this message]
2020-09-30 18:04 ` [PATCH 02/16] target/mips: Move cpu_mips_get_random() with CP0 helpers Aleksandar Markovic
2020-09-28 17:15 ` [PATCH 03/16] target/mips/cp0_timer: Explicit unit in variable name Philippe Mathieu-Daudé
2020-09-30 18:10 ` Aleksandar Markovic
2020-09-28 17:15 ` [PATCH 04/16] target/mips/cpu: Introduce mips_cpu_properties[] Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 05/16] target/mips/cpu: Set default CPU frequency to 200 MHz Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 06/16] target/mips: Keep CP0 counter in sync with the CPU frequency Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 07/16] hw/mips/r4k: Explicit CPU frequency is 200 MHz Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 08/16] hw/mips/fuloong2e: Set CPU frequency to 533 MHz Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 09/16] hw/mips/mipssim: Correct CPU frequency Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 10/16] hw/mips/jazz: Correct CPU frequencies Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 11/16] hw/mips/cps: Expose input clock and connect it to CPU cores Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 12/16] hw/mips/boston: Set CPU frequency to 1 GHz Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 13/16] hw/mips/malta: Set CPU frequency to 320 MHz Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 14/16] hw/mips/cps: Do not allow use without input clock Philippe Mathieu-Daudé
2020-09-28 17:15 ` [PATCH 15/16] target/mips/cpu: Do not allow system-mode " Philippe Mathieu-Daudé
2020-09-29 13:01 ` Igor Mammedov
2020-09-29 14:40 ` Philippe Mathieu-Daudé
2020-10-05 7:39 ` Philippe Mathieu-Daudé
2020-10-05 16:25 ` Igor Mammedov
2020-09-28 17:15 ` [PATCH 16/16] tests/acceptance: Test the MIPSsim machine Philippe Mathieu-Daudé
2020-09-28 20:33 ` Willian Rampazzo
2020-09-29 9:09 ` Philippe Mathieu-Daudé
2020-09-29 9:38 ` Alex Bennée
2020-09-29 9:50 ` Philippe Mathieu-Daudé
2020-09-30 8:43 ` Daniel P. Berrangé
2020-09-30 9:49 ` Alex Bennée
2020-09-30 10:08 ` Philippe Mathieu-Daudé
2020-09-29 2:46 ` [PATCH 00/16] hw/mips: Set CPU frequency no-reply
2020-09-29 8:58 ` Philippe Mathieu-Daudé
2020-09-30 7:40 ` Igor Mammedov
2020-09-30 10:13 ` Philippe Mathieu-Daudé
2020-10-09 15:40 ` Philippe Mathieu-Daudé
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