From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v13 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c
Date: Wed, 14 Apr 2021 13:26:10 +0200 [thread overview]
Message-ID: <20210414112650.18003-41-cfontana@suse.de> (raw)
In-Reply-To: <20210414112650.18003-1-cfontana@suse.de>
move the TCGCPUOps interface to tcg/tcg-cpu.c
in preparation for the addition of the TCG accel-cpu class.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
---
target/arm/cpu.h | 1 -
target/arm/internals.h | 5 -
target/arm/tcg/tcg-cpu.h | 6 +
target/arm/cpu-sysemu.c | 4 +
target/arm/cpu.c | 209 +--------------------------------
target/arm/cpu_tcg.c | 2 +-
target/arm/tcg/helper.c | 1 +
target/arm/tcg/tcg-cpu.c | 229 +++++++++++++++++++++++++++++++++++++
target/arm/tcg/meson.build | 1 +
9 files changed, 244 insertions(+), 214 deletions(-)
create mode 100644 target/arm/tcg/tcg-cpu.c
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 30882bfbb6..3e92f4faaa 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1024,7 +1024,6 @@ extern const VMStateDescription vmstate_arm_cpu;
void arm_cpu_do_interrupt(CPUState *cpu);
void arm_v7m_cpu_do_interrupt(CPUState *cpu);
-bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
int arm_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/arm/internals.h b/target/arm/internals.h
index e137bb0ac0..811e029f83 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -172,11 +172,6 @@ static inline int r14_bank_number(int mode)
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
void arm_translate_init(void);
-#ifdef CONFIG_TCG
-void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-#endif /* CONFIG_TCG */
-
-
enum arm_fprounding {
FPROUNDING_TIEEVEN,
FPROUNDING_POSINF,
diff --git a/target/arm/tcg/tcg-cpu.h b/target/arm/tcg/tcg-cpu.h
index 7e62f92d16..d93c6a6749 100644
--- a/target/arm/tcg/tcg-cpu.h
+++ b/target/arm/tcg/tcg-cpu.h
@@ -21,6 +21,12 @@
#define ARM_TCG_CPU_H
#include "cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb);
+
+extern struct TCGCPUOps arm_tcg_ops;
#ifndef CONFIG_USER_ONLY
/* Do semihosting call and set the appropriate return value. */
diff --git a/target/arm/cpu-sysemu.c b/target/arm/cpu-sysemu.c
index e83d55b9f7..c09c89eeac 100644
--- a/target/arm/cpu-sysemu.c
+++ b/target/arm/cpu-sysemu.c
@@ -28,6 +28,10 @@
#include "sysemu/tcg.h"
#include "tcg/tcg-cpu.h"
+#ifdef CONFIG_TCG
+#include "tcg/tcg-cpu.h"
+#endif /* CONFIG_TCG */
+
void arm_cpu_set_irq(void *opaque, int irq, int level)
{
ARMCPU *cpu = opaque;
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e9dc5da4ca..b130f56d98 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -27,7 +27,7 @@
#include "cpu.h"
#include "cpregs.h"
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg-cpu.h"
#endif /* CONFIG_TCG */
#include "cpu32.h"
#include "internals.h"
@@ -59,25 +59,6 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
}
}
-#ifdef CONFIG_TCG
-void arm_cpu_synchronize_from_tb(CPUState *cs,
- const TranslationBlock *tb)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
- /*
- * It's OK to look at env for the current mode here, because it's
- * never possible for an AArch64 TB to chain to an AArch32 TB.
- */
- if (is_a64(env)) {
- env->pc = tb->pc;
- } else {
- env->regs[15] = tb->pc;
- }
-}
-#endif /* CONFIG_TCG */
-
static bool arm_cpu_has_work(CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -443,175 +424,6 @@ static void arm_cpu_reset(DeviceState *dev)
}
}
-static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
- unsigned int target_el,
- unsigned int cur_el, bool secure,
- uint64_t hcr_el2)
-{
- CPUARMState *env = cs->env_ptr;
- bool pstate_unmasked;
- bool unmasked = false;
-
- /*
- * Don't take exceptions if they target a lower EL.
- * This check should catch any exceptions that would not be taken
- * but left pending.
- */
- if (cur_el > target_el) {
- return false;
- }
-
- switch (excp_idx) {
- case EXCP_FIQ:
- pstate_unmasked = !(env->daif & PSTATE_F);
- break;
-
- case EXCP_IRQ:
- pstate_unmasked = !(env->daif & PSTATE_I);
- break;
-
- case EXCP_VFIQ:
- if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
- /* VFIQs are only taken when hypervized. */
- return false;
- }
- return !(env->daif & PSTATE_F);
- case EXCP_VIRQ:
- if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
- /* VIRQs are only taken when hypervized. */
- return false;
- }
- return !(env->daif & PSTATE_I);
- default:
- g_assert_not_reached();
- }
-
- /*
- * Use the target EL, current execution state and SCR/HCR settings to
- * determine whether the corresponding CPSR bit is used to mask the
- * interrupt.
- */
- if ((target_el > cur_el) && (target_el != 1)) {
- /* Exceptions targeting a higher EL may not be maskable */
- if (arm_feature(env, ARM_FEATURE_AARCH64)) {
- /*
- * 64-bit masking rules are simple: exceptions to EL3
- * can't be masked, and exceptions to EL2 can only be
- * masked from Secure state. The HCR and SCR settings
- * don't affect the masking logic, only the interrupt routing.
- */
- if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
- unmasked = true;
- }
- } else {
- /*
- * The old 32-bit-only environment has a more complicated
- * masking setup. HCR and SCR bits not only affect interrupt
- * routing but also change the behaviour of masking.
- */
- bool hcr, scr;
-
- switch (excp_idx) {
- case EXCP_FIQ:
- /*
- * If FIQs are routed to EL3 or EL2 then there are cases where
- * we override the CPSR.F in determining if the exception is
- * masked or not. If neither of these are set then we fall back
- * to the CPSR.F setting otherwise we further assess the state
- * below.
- */
- hcr = hcr_el2 & HCR_FMO;
- scr = (env->cp15.scr_el3 & SCR_FIQ);
-
- /*
- * When EL3 is 32-bit, the SCR.FW bit controls whether the
- * CPSR.F bit masks FIQ interrupts when taken in non-secure
- * state. If SCR.FW is set then FIQs can be masked by CPSR.F
- * when non-secure but only when FIQs are only routed to EL3.
- */
- scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
- break;
- case EXCP_IRQ:
- /*
- * When EL3 execution state is 32-bit, if HCR.IMO is set then
- * we may override the CPSR.I masking when in non-secure state.
- * The SCR.IRQ setting has already been taken into consideration
- * when setting the target EL, so it does not have a further
- * affect here.
- */
- hcr = hcr_el2 & HCR_IMO;
- scr = false;
- break;
- default:
- g_assert_not_reached();
- }
-
- if ((scr || hcr) && !secure) {
- unmasked = true;
- }
- }
- }
-
- /*
- * The PSTATE bits only mask the interrupt if we have not overriden the
- * ability above.
- */
- return unmasked || pstate_unmasked;
-}
-
-bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
-{
- CPUClass *cc = CPU_GET_CLASS(cs);
- CPUARMState *env = cs->env_ptr;
- uint32_t cur_el = arm_current_el(env);
- bool secure = arm_is_secure(env);
- uint64_t hcr_el2 = arm_hcr_el2_eff(env);
- uint32_t target_el;
- uint32_t excp_idx;
-
- /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
-
- if (interrupt_request & CPU_INTERRUPT_FIQ) {
- excp_idx = EXCP_FIQ;
- target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el,
- cur_el, secure, hcr_el2)) {
- goto found;
- }
- }
- if (interrupt_request & CPU_INTERRUPT_HARD) {
- excp_idx = EXCP_IRQ;
- target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
- if (arm_excp_unmasked(cs, excp_idx, target_el,
- cur_el, secure, hcr_el2)) {
- goto found;
- }
- }
- if (interrupt_request & CPU_INTERRUPT_VIRQ) {
- excp_idx = EXCP_VIRQ;
- target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el,
- cur_el, secure, hcr_el2)) {
- goto found;
- }
- }
- if (interrupt_request & CPU_INTERRUPT_VFIQ) {
- excp_idx = EXCP_VFIQ;
- target_el = 1;
- if (arm_excp_unmasked(cs, excp_idx, target_el,
- cur_el, secure, hcr_el2)) {
- goto found;
- }
- }
- return false;
-
- found:
- cs->exception_index = excp_idx;
- env->exception.target_el = target_el;
- cc->tcg_ops->do_interrupt(cs);
- return true;
-}
-
void arm_cpu_update_virq(ARMCPU *cpu)
{
/*
@@ -1016,6 +828,7 @@ static void arm_cpu_finalizefn(Object *obj)
QLIST_REMOVE(hook, node);
g_free(hook);
}
+
#ifndef CONFIG_USER_ONLY
if (cpu->pmu_timer) {
timer_free(cpu->pmu_timer);
@@ -1631,24 +1444,6 @@ static Property arm_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST()
};
-#ifdef CONFIG_TCG
-static struct TCGCPUOps arm_tcg_ops = {
- .initialize = arm_translate_init,
- .synchronize_from_tb = arm_cpu_synchronize_from_tb,
- .cpu_exec_interrupt = arm_cpu_exec_interrupt,
- .tlb_fill = arm_cpu_tlb_fill,
- .debug_excp_handler = arm_debug_excp_handler,
-
-#if !defined(CONFIG_USER_ONLY)
- .do_interrupt = arm_cpu_do_interrupt,
- .do_transaction_failed = arm_cpu_do_transaction_failed,
- .do_unaligned_access = arm_cpu_do_unaligned_access,
- .adjust_watchpoint_address = arm_adjust_watchpoint_address,
- .debug_check_watchpoint = arm_debug_check_watchpoint,
-#endif /* !CONFIG_USER_ONLY */
-};
-#endif /* CONFIG_TCG */
-
static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index d120250b18..54df5a8e77 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -11,7 +11,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#ifdef CONFIG_TCG
-#include "hw/core/tcg-cpu-ops.h"
+#include "tcg/tcg-cpu.h"
#endif /* CONFIG_TCG */
#include "internals.h"
#include "target/arm/idau.h"
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index bb313dfba1..8a0d59cbad 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -16,6 +16,7 @@
#include "arm_ldst.h"
#include "cpu-mmu.h"
#include "cpregs.h"
+#include "tcg-cpu.h"
static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
{
diff --git a/target/arm/tcg/tcg-cpu.c b/target/arm/tcg/tcg-cpu.c
new file mode 100644
index 0000000000..9fd996d908
--- /dev/null
+++ b/target/arm/tcg/tcg-cpu.c
@@ -0,0 +1,229 @@
+/*
+ * QEMU ARM CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see
+ * <http://www.gnu.org/licenses/gpl-2.0.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg-cpu.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "cpregs.h"
+#include "internals.h"
+#include "exec/exec-all.h"
+
+void arm_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
+ /*
+ * It's OK to look at env for the current mode here, because it's
+ * never possible for an AArch64 TB to chain to an AArch32 TB.
+ */
+ if (is_a64(env)) {
+ env->pc = tb->pc;
+ } else {
+ env->regs[15] = tb->pc;
+ }
+}
+
+static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
+ unsigned int target_el,
+ unsigned int cur_el, bool secure,
+ uint64_t hcr_el2)
+{
+ CPUARMState *env = cs->env_ptr;
+ bool pstate_unmasked;
+ bool unmasked = false;
+
+ /*
+ * Don't take exceptions if they target a lower EL.
+ * This check should catch any exceptions that would not be taken
+ * but left pending.
+ */
+ if (cur_el > target_el) {
+ return false;
+ }
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ pstate_unmasked = !(env->daif & PSTATE_F);
+ break;
+
+ case EXCP_IRQ:
+ pstate_unmasked = !(env->daif & PSTATE_I);
+ break;
+
+ case EXCP_VFIQ:
+ if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
+ /* VFIQs are only taken when hypervized. */
+ return false;
+ }
+ return !(env->daif & PSTATE_F);
+ case EXCP_VIRQ:
+ if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
+ /* VIRQs are only taken when hypervized. */
+ return false;
+ }
+ return !(env->daif & PSTATE_I);
+ default:
+ g_assert_not_reached();
+ }
+
+ /*
+ * Use the target EL, current execution state and SCR/HCR settings to
+ * determine whether the corresponding CPSR bit is used to mask the
+ * interrupt.
+ */
+ if ((target_el > cur_el) && (target_el != 1)) {
+ /* Exceptions targeting a higher EL may not be maskable */
+ if (arm_feature(env, ARM_FEATURE_AARCH64)) {
+ /*
+ * 64-bit masking rules are simple: exceptions to EL3
+ * can't be masked, and exceptions to EL2 can only be
+ * masked from Secure state. The HCR and SCR settings
+ * don't affect the masking logic, only the interrupt routing.
+ */
+ if (target_el == 3 || !secure || (env->cp15.scr_el3 & SCR_EEL2)) {
+ unmasked = true;
+ }
+ } else {
+ /*
+ * The old 32-bit-only environment has a more complicated
+ * masking setup. HCR and SCR bits not only affect interrupt
+ * routing but also change the behaviour of masking.
+ */
+ bool hcr, scr;
+
+ switch (excp_idx) {
+ case EXCP_FIQ:
+ /*
+ * If FIQs are routed to EL3 or EL2 then there are cases where
+ * we override the CPSR.F in determining if the exception is
+ * masked or not. If neither of these are set then we fall back
+ * to the CPSR.F setting otherwise we further assess the state
+ * below.
+ */
+ hcr = hcr_el2 & HCR_FMO;
+ scr = (env->cp15.scr_el3 & SCR_FIQ);
+
+ /*
+ * When EL3 is 32-bit, the SCR.FW bit controls whether the
+ * CPSR.F bit masks FIQ interrupts when taken in non-secure
+ * state. If SCR.FW is set then FIQs can be masked by CPSR.F
+ * when non-secure but only when FIQs are only routed to EL3.
+ */
+ scr = scr && !((env->cp15.scr_el3 & SCR_FW) && !hcr);
+ break;
+ case EXCP_IRQ:
+ /*
+ * When EL3 execution state is 32-bit, if HCR.IMO is set then
+ * we may override the CPSR.I masking when in non-secure state.
+ * The SCR.IRQ setting has already been taken into consideration
+ * when setting the target EL, so it does not have a further
+ * affect here.
+ */
+ hcr = hcr_el2 & HCR_IMO;
+ scr = false;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if ((scr || hcr) && !secure) {
+ unmasked = true;
+ }
+ }
+ }
+
+ /*
+ * The PSTATE bits only mask the interrupt if we have not overriden the
+ * ability above.
+ */
+ return unmasked || pstate_unmasked;
+}
+
+static bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+ CPUClass *cc = CPU_GET_CLASS(cs);
+ CPUARMState *env = cs->env_ptr;
+ uint32_t cur_el = arm_current_el(env);
+ bool secure = arm_is_secure(env);
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+ uint32_t target_el;
+ uint32_t excp_idx;
+
+ /* The prioritization of interrupts is IMPLEMENTATION DEFINED. */
+
+ if (interrupt_request & CPU_INTERRUPT_FIQ) {
+ excp_idx = EXCP_FIQ;
+ target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
+ goto found;
+ }
+ }
+ if (interrupt_request & CPU_INTERRUPT_HARD) {
+ excp_idx = EXCP_IRQ;
+ target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
+ goto found;
+ }
+ }
+ if (interrupt_request & CPU_INTERRUPT_VIRQ) {
+ excp_idx = EXCP_VIRQ;
+ target_el = 1;
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
+ goto found;
+ }
+ }
+ if (interrupt_request & CPU_INTERRUPT_VFIQ) {
+ excp_idx = EXCP_VFIQ;
+ target_el = 1;
+ if (arm_excp_unmasked(cs, excp_idx, target_el,
+ cur_el, secure, hcr_el2)) {
+ goto found;
+ }
+ }
+ return false;
+
+ found:
+ cs->exception_index = excp_idx;
+ env->exception.target_el = target_el;
+ cc->tcg_ops->do_interrupt(cs);
+ return true;
+}
+
+struct TCGCPUOps arm_tcg_ops = {
+ .initialize = arm_translate_init,
+ .synchronize_from_tb = arm_cpu_synchronize_from_tb,
+ .cpu_exec_interrupt = arm_cpu_exec_interrupt,
+ .tlb_fill = arm_cpu_tlb_fill,
+ .debug_excp_handler = arm_debug_excp_handler,
+
+#if !defined(CONFIG_USER_ONLY)
+ .do_interrupt = arm_cpu_do_interrupt,
+ .do_transaction_failed = arm_cpu_do_transaction_failed,
+ .do_unaligned_access = arm_cpu_do_unaligned_access,
+ .adjust_watchpoint_address = arm_adjust_watchpoint_address,
+ .debug_check_watchpoint = arm_debug_check_watchpoint,
+#endif /* !CONFIG_USER_ONLY */
+};
diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build
index b1a2eadda4..cb67c59416 100644
--- a/target/arm/tcg/meson.build
+++ b/target/arm/tcg/meson.build
@@ -28,6 +28,7 @@ arm_ss.add(when: 'CONFIG_TCG', if_true: files(
'vfp_helper.c',
'crypto_helper.c',
'debug_helper.c',
+ 'tcg-cpu.c',
), if_false: files(
'tcg-stubs.c',
--
2.26.2
next prev parent reply other threads:[~2021-04-14 11:58 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 11:25 [RFC v13 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-14 11:25 ` [RFC v13 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-14 11:25 ` [RFC v13 02/80] target/arm: move helpers " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-14 11:25 ` [RFC v13 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-14 11:25 ` [RFC v13 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-14 11:25 ` [RFC v13 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-14 11:25 ` [RFC v13 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-14 11:25 ` [RFC v13 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-14 11:25 ` [RFC v13 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-14 11:25 ` [RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-14 11:25 ` [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state Claudio Fontana
2021-04-14 11:25 ` [RFC v13 29/80] target/arm: move a15 cpu model away from the TCG-only models Claudio Fontana
2021-04-14 11:26 ` [RFC v13 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-14 11:26 ` [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-14 11:26 ` [RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-14 11:26 ` Claudio Fontana [this message]
2021-04-14 11:26 ` [RFC v13 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-14 11:26 ` [RFC v13 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-14 11:26 ` [RFC v13 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-14 11:26 ` [RFC v13 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-14 11:26 ` [RFC v13 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-14 11:26 ` [RFC v13 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-14 11:26 ` [RFC v13 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-14 11:26 ` [RFC v13 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-14 11:26 ` [RFC v13 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-14 11:26 ` [RFC v13 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-14 11:26 ` [RFC v13 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-14 11:26 ` [RFC v13 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-14 11:26 ` [RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-14 11:26 ` [RFC v13 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions Claudio Fontana
2021-04-14 11:26 ` [RFC v13 69/80] target/arm: tcg-sve: rename the " Claudio Fontana
2021-04-14 11:26 ` [RFC v13 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-14 11:26 ` [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-14 11:26 ` [RFC v13 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-14 11:26 ` [RFC v13 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-14 11:26 ` [RFC v13 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
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