From: Claudio Fontana <cfontana@suse.de>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Roman Bolshakov <r.bolshakov@yadro.com>,
Claudio Fontana <cfontana@suse.de>,
Eduardo Habkost <ehabkost@redhat.com>,
qemu-devel@nongnu.org
Subject: [RFC v13 68/80] target/arm: tcg-sve: import narrow_vq and change_el functions
Date: Wed, 14 Apr 2021 13:26:38 +0200 [thread overview]
Message-ID: <20210414112650.18003-69-cfontana@suse.de> (raw)
In-Reply-To: <20210414112650.18003-1-cfontana@suse.de>
aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related
functions only used for TCG, so we can put them in the
tcg-sve.c module.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 7 ---
target/arm/tcg/tcg-sve.h | 5 ++
linux-user/syscall.c | 4 ++
target/arm/cpu-exceptions-aa64.c | 1 +
target/arm/tcg/cpregs.c | 4 ++
target/arm/tcg/helper-a64.c | 1 +
target/arm/tcg/helper.c | 87 --------------------------------
target/arm/tcg/tcg-sve.c | 86 +++++++++++++++++++++++++++++++
8 files changed, 101 insertions(+), 94 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 204fc13949..f12650bd0b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1049,9 +1049,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
#ifdef TARGET_AARCH64
int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64);
static inline bool is_a64(CPUARMState *env)
{
@@ -1083,10 +1080,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
}
#else
-static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
-static inline void aarch64_sve_change_el(CPUARMState *env, int o,
- int n, bool a)
-{ }
#define is_a64(env) ((void)env, false)
diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h
index 4bed809b9a..5855bb4289 100644
--- a/target/arm/tcg/tcg-sve.h
+++ b/target/arm/tcg/tcg-sve.h
@@ -21,4 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map,
bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
Error **errp);
+void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
+
+void aarch64_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64);
+
#endif /* TCG_SVE_H */
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 95d79ddc43..d935a98e2f 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -134,6 +134,10 @@
#include "fd-trans.h"
#include "tcg/tcg.h"
+#ifdef TARGET_AARCH64
+#include "tcg/tcg-sve.h"
+#endif /* TARGET_AARCH64 */
+
#ifndef CLONE_IO
#define CLONE_IO 0x80000000 /* Clone io context */
#endif
diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c
index 7daaba0426..adaf3bab17 100644
--- a/target/arm/cpu-exceptions-aa64.c
+++ b/target/arm/cpu-exceptions-aa64.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "cpu.h"
+#include "tcg/tcg-sve.h"
#include "internals.h"
#include "sysemu/tcg.h"
diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c
index f2698c72a9..5c5915574e 100644
--- a/target/arm/tcg/cpregs.c
+++ b/target/arm/tcg/cpregs.c
@@ -16,6 +16,10 @@
#include "cpu-mmu.h"
#include "cpregs.h"
+#ifdef TARGET_AARCH64
+#include "tcg/tcg-sve.h"
+#endif /* TARGET_AARCH64 */
+
#define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
#define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */
diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c
index 061c8ff846..18d4809c23 100644
--- a/target/arm/tcg/helper-a64.c
+++ b/target/arm/tcg/helper-a64.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "cpu.h"
+#include "tcg/tcg-sve.h"
#include "exec/gdbstub.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c
index eb0fd394da..80df9af690 100644
--- a/target/arm/tcg/helper.c
+++ b/target/arm/tcg/helper.c
@@ -1280,90 +1280,3 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
*pflags = flags;
}
-
-#ifdef TARGET_AARCH64
-/*
- * The manual says that when SVE is enabled and VQ is widened the
- * implementation is allowed to zero the previously inaccessible
- * portion of the registers. The corollary to that is that when
- * SVE is enabled and VQ is narrowed we are also allowed to zero
- * the now inaccessible portion of the registers.
- *
- * The intent of this is that no predicate bit beyond VQ is ever set.
- * Which means that some operations on predicate registers themselves
- * may operate on full uint64_t or even unrolled across the maximum
- * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
- * may well be cheaper than conditionals to restrict the operation
- * to the relevant portion of a uint16_t[16].
- */
-void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
-{
- int i, j;
- uint64_t pmask;
-
- assert(vq >= 1 && vq <= ARM_MAX_VQ);
- assert(vq <= env_archcpu(env)->sve_max_vq);
-
- /* Zap the high bits of the zregs. */
- for (i = 0; i < 32; i++) {
- memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
- }
-
- /* Zap the high bits of the pregs and ffr. */
- pmask = 0;
- if (vq & 3) {
- pmask = ~(-1ULL << (16 * (vq & 3)));
- }
- for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
- for (i = 0; i < 17; ++i) {
- env->vfp.pregs[i].p[j] &= pmask;
- }
- pmask = 0;
- }
-}
-
-/*
- * Notice a change in SVE vector size when changing EL.
- */
-void aarch64_sve_change_el(CPUARMState *env, int old_el,
- int new_el, bool el0_a64)
-{
- ARMCPU *cpu = env_archcpu(env);
- int old_len, new_len;
- bool old_a64, new_a64;
-
- /* Nothing to do if no SVE. */
- if (!cpu_isar_feature(aa64_sve, cpu)) {
- return;
- }
-
- /* Nothing to do if FP is disabled in either EL. */
- if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
- return;
- }
-
- /*
- * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
- * at ELx, or not available because the EL is in AArch32 state, then
- * for all purposes other than a direct read, the ZCR_ELx.LEN field
- * has an effective value of 0".
- *
- * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
- * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
- * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
- * we already have the correct register contents when encountering the
- * vq0->vq0 transition between EL0->EL1.
- */
- old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
- old_len = (old_a64 && !sve_exception_el(env, old_el)
- ? sve_zcr_len_for_el(env, old_el) : 0);
- new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
- new_len = (new_a64 && !sve_exception_el(env, new_el)
- ? sve_zcr_len_for_el(env, new_el) : 0);
-
- /* When changing vector length, clear inaccessible state. */
- if (new_len < old_len) {
- aarch64_sve_narrow_vq(env, new_len + 1);
- }
-}
-#endif
diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c
index 99cfde1f41..908d2c2f2c 100644
--- a/target/arm/tcg/tcg-sve.c
+++ b/target/arm/tcg/tcg-sve.c
@@ -24,6 +24,7 @@
#include "sysemu/tcg.h"
#include "cpu-sve.h"
#include "tcg-sve.h"
+#include "cpu-exceptions-aa64.h"
void tcg_sve_enable_lens(unsigned long *sve_vq_map,
unsigned long *sve_vq_init, uint32_t max_vq)
@@ -79,3 +80,88 @@ bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq,
}
return true;
}
+
+/*
+ * The manual says that when SVE is enabled and VQ is widened the
+ * implementation is allowed to zero the previously inaccessible
+ * portion of the registers. The corollary to that is that when
+ * SVE is enabled and VQ is narrowed we are also allowed to zero
+ * the now inaccessible portion of the registers.
+ *
+ * The intent of this is that no predicate bit beyond VQ is ever set.
+ * Which means that some operations on predicate registers themselves
+ * may operate on full uint64_t or even unrolled across the maximum
+ * uint64_t[4]. Performing 4 bits of host arithmetic unconditionally
+ * may well be cheaper than conditionals to restrict the operation
+ * to the relevant portion of a uint16_t[16].
+ */
+void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq)
+{
+ int i, j;
+ uint64_t pmask;
+
+ assert(vq >= 1 && vq <= ARM_MAX_VQ);
+ assert(vq <= env_archcpu(env)->sve_max_vq);
+
+ /* Zap the high bits of the zregs. */
+ for (i = 0; i < 32; i++) {
+ memset(&env->vfp.zregs[i].d[2 * vq], 0, 16 * (ARM_MAX_VQ - vq));
+ }
+
+ /* Zap the high bits of the pregs and ffr. */
+ pmask = 0;
+ if (vq & 3) {
+ pmask = ~(-1ULL << (16 * (vq & 3)));
+ }
+ for (j = vq / 4; j < ARM_MAX_VQ / 4; j++) {
+ for (i = 0; i < 17; ++i) {
+ env->vfp.pregs[i].p[j] &= pmask;
+ }
+ pmask = 0;
+ }
+}
+
+/*
+ * Notice a change in SVE vector size when changing EL.
+ */
+void aarch64_sve_change_el(CPUARMState *env, int old_el,
+ int new_el, bool el0_a64)
+{
+ ARMCPU *cpu = env_archcpu(env);
+ int old_len, new_len;
+ bool old_a64, new_a64;
+
+ /* Nothing to do if no SVE. */
+ if (!cpu_isar_feature(aa64_sve, cpu)) {
+ return;
+ }
+
+ /* Nothing to do if FP is disabled in either EL. */
+ if (fp_exception_el(env, old_el) || fp_exception_el(env, new_el)) {
+ return;
+ }
+
+ /*
+ * DDI0584A.d sec 3.2: "If SVE instructions are disabled or trapped
+ * at ELx, or not available because the EL is in AArch32 state, then
+ * for all purposes other than a direct read, the ZCR_ELx.LEN field
+ * has an effective value of 0".
+ *
+ * Consider EL2 (aa64, vq=4) -> EL0 (aa32) -> EL1 (aa64, vq=0).
+ * If we ignore aa32 state, we would fail to see the vq4->vq0 transition
+ * from EL2->EL1. Thus we go ahead and narrow when entering aa32 so that
+ * we already have the correct register contents when encountering the
+ * vq0->vq0 transition between EL0->EL1.
+ */
+ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64;
+ old_len = (old_a64 && !sve_exception_el(env, old_el)
+ ? sve_zcr_len_for_el(env, old_el) : 0);
+ new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64;
+ new_len = (new_a64 && !sve_exception_el(env, new_el)
+ ? sve_zcr_len_for_el(env, new_el) : 0);
+
+ /* When changing vector length, clear inaccessible state. */
+ if (new_len < old_len) {
+ aarch64_sve_narrow_vq(env, new_len + 1);
+ }
+}
--
2.26.2
next prev parent reply other threads:[~2021-04-14 12:19 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-14 11:25 [RFC v13 00/80] arm cleanup experiment for kvm-only build Claudio Fontana
2021-04-14 11:25 ` [RFC v13 01/80] target/arm: move translate modules to tcg/ Claudio Fontana
2021-04-14 11:25 ` [RFC v13 02/80] target/arm: move helpers " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 03/80] arm: tcg: only build under CONFIG_TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 04/80] target/arm: tcg: add sysemu and user subdirs Claudio Fontana
2021-04-14 11:25 ` [RFC v13 05/80] target/arm: tcg: split mte_helper user-only and sysemu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 06/80] target/arm: tcg: move sysemu-only parts of debug_helper Claudio Fontana
2021-04-14 11:25 ` [RFC v13 07/80] target/arm: tcg: split tlb_helper user-only and sysemu-only parts Claudio Fontana
2021-04-14 11:25 ` [RFC v13 08/80] target/arm: tcg: split m_helper " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 09/80] target/arm: only build psci for TCG Claudio Fontana
2021-04-14 11:25 ` [RFC v13 10/80] target/arm: split off cpu-sysemu.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 11/80] target/arm: tcg: fix comment style before move to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 12/80] target/arm: move physical address translation " Claudio Fontana
2021-04-14 11:25 ` [RFC v13 13/80] target/arm: fix style in preparation of new cpregs module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 14/80] target/arm: split cpregs from tcg/helper.c Claudio Fontana
2021-04-14 11:25 ` [RFC v13 15/80] target/arm: move cpu definitions to common cpu module Claudio Fontana
2021-04-14 11:25 ` [RFC v13 16/80] target/arm: only perform TCG cpu and machine inits if TCG enabled Claudio Fontana
2021-04-14 11:25 ` [RFC v13 17/80] target/arm: tcg: add stubs for some helpers for non-tcg builds Claudio Fontana
2021-04-14 11:25 ` [RFC v13 18/80] target/arm: move cpsr_read, cpsr_write to cpu_common Claudio Fontana
2021-04-14 11:25 ` [RFC v13 19/80] target/arm: add temporary stub for arm_rebuild_hflags Claudio Fontana
2021-04-14 11:25 ` [RFC v13 20/80] target/arm: move arm_hcr_el2_eff from tcg/ to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 21/80] target/arm: split vfp state setting from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 22/80] target/arm: move arm_mmu_idx* to cpu-mmu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 23/80] target/arm: move sve_zcr_len_for_el to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 24/80] target/arm: move arm_sctlr away from tcg helpers Claudio Fontana
2021-04-14 11:25 ` [RFC v13 25/80] target/arm: move arm_cpu_list to common_cpu Claudio Fontana
2021-04-14 11:25 ` [RFC v13 26/80] target/arm: move aarch64_sync_32_to_64 (and vv) to cpu code Claudio Fontana
2021-04-14 11:25 ` [RFC v13 27/80] target/arm: new cpu32 ARM 32 bit CPU Class Claudio Fontana
2021-04-14 11:25 ` [RFC v13 28/80] target/arm: split 32bit and 64bit arm dump state Claudio Fontana
2021-04-14 11:25 ` [RFC v13 29/80] target/arm: move a15 cpu model away from the TCG-only models Claudio Fontana
2021-04-14 11:26 ` [RFC v13 30/80] target/arm: fixup sve_exception_el code style before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 31/80] target/arm: move sve_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 32/80] target/arm: fix comments style of fp_exception_el before moving it Claudio Fontana
2021-04-14 11:26 ` [RFC v13 33/80] target/arm: move fp_exception_el out of TCG helpers Claudio Fontana
2021-04-14 11:26 ` [RFC v13 34/80] target/arm: remove now useless ifndef from fp_exception_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 35/80] target/arm: make further preparation for the exception code to move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 36/80] target/arm: fix style of arm_cpu_do_interrupt functions before move Claudio Fontana
2021-04-14 11:26 ` [RFC v13 37/80] target/arm: move exception code out of tcg/helper.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 38/80] target/arm: rename handle_semihosting to tcg_handle_semihosting Claudio Fontana
2021-04-14 11:26 ` [RFC v13 39/80] target/arm: replace CONFIG_TCG with tcg_enabled Claudio Fontana
2021-04-14 11:26 ` [RFC v13 40/80] target/arm: move TCGCPUOps to tcg/tcg-cpu.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 41/80] target/arm: move cpu_tcg to tcg/tcg-cpu-models.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 42/80] target/arm: wrap call to aarch64_sve_change_el in tcg_enabled() Claudio Fontana
2021-04-14 11:26 ` [RFC v13 43/80] target/arm: remove kvm include file for PSCI and arm-powerctl Claudio Fontana
2021-04-14 11:26 ` [RFC v13 44/80] target/arm: move kvm-const.h, kvm.c, kvm64.c, kvm_arm.h to kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 45/80] MAINTAINERS: update arm kvm maintained files to all in target/arm/kvm/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 46/80] target/arm: cleanup cpu includes Claudio Fontana
2021-04-14 11:26 ` [RFC v13 47/80] target/arm: remove broad "else" statements when checking accels Claudio Fontana
2021-04-14 11:26 ` [RFC v13 48/80] target/arm: remove kvm-stub.c Claudio Fontana
2021-04-14 11:26 ` [RFC v13 49/80] tests/qtest: skip bios-tables-test test_acpi_oem_fields_virt for KVM Claudio Fontana
2021-04-14 11:26 ` [RFC v13 50/80] tests: restrict TCG-only arm-cpu-features tests to TCG builds Claudio Fontana
2021-04-14 11:26 ` [RFC v13 51/80] tests: do not run test-hmp on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 52/80] tests: device-introspect-test: cope with ARM TCG-only devices Claudio Fontana
2021-04-14 11:26 ` [RFC v13 53/80] tests: do not run qom-test on all machines for ARM KVM-only Claudio Fontana
2021-04-14 11:26 ` [RFC v13 54/80] Revert "target/arm: Restrict v8M IDAU to TCG" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 55/80] target/arm: create kvm cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 56/80] target/arm: move kvm post init initialization to kvm cpu accel Claudio Fontana
2021-04-14 11:26 ` [RFC v13 57/80] target/arm: add tcg cpu accel class Claudio Fontana
2021-04-14 11:26 ` [RFC v13 58/80] target/arm: move TCG gt timer creation code in tcg/ Claudio Fontana
2021-04-14 11:26 ` [RFC v13 59/80] target/arm: cpu-sve: new module Claudio Fontana
2021-04-14 11:26 ` [RFC v13 60/80] target/arm: cpu-sve: rename functions according to module prefix Claudio Fontana
2021-04-14 11:26 ` [RFC v13 61/80] target/arm: cpu-sve: split TCG and KVM functionality Claudio Fontana
2021-04-14 11:26 ` [RFC v13 62/80] target/arm: cpu-sve: make cpu_sve_finalize_features return bool Claudio Fontana
2021-04-14 11:26 ` [RFC v13 63/80] target/arm: make is_aa64 and arm_el_is_aa64 a macro for !TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 64/80] target/arm: restrict rebuild_hflags_a64 to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 65/80] target/arm: arch_dump: restrict ELFCLASS64 to AArch64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 66/80] target/arm: cpu-exceptions, cpu-exceptions-aa64: new modules Claudio Fontana
2021-04-14 11:26 ` [RFC v13 67/80] target/arm: tcg: restrict ZCR cpregs to TARGET_AARCH64 Claudio Fontana
2021-04-14 11:26 ` Claudio Fontana [this message]
2021-04-14 11:26 ` [RFC v13 69/80] target/arm: tcg-sve: rename the narrow_vq and change_el functions Claudio Fontana
2021-04-14 11:26 ` [RFC v13 70/80] target/arm: move sve_zcr_len_for_el to TARGET_AARCH64-only cpu-sve Claudio Fontana
2021-04-14 11:26 ` [RFC v13 71/80] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Claudio Fontana
2021-04-14 11:26 ` [RFC v13 72/80] target/arm: cpu-common: wrap a64-only check with is_a64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 73/80] target/arm: cpu-pauth: new module for ARMv8.3 Pointer Authentication Claudio Fontana
2021-04-14 11:26 ` [RFC v13 74/80] target/arm: cpu-pauth: change arm_cpu_pauth_finalize name and sig Claudio Fontana
2021-04-14 11:26 ` [RFC v13 75/80] target/arm: move arm_cpu_finalize_features into cpu64 Claudio Fontana
2021-04-14 11:26 ` [RFC v13 76/80] target/arm: cpu64: rename arm_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 77/80] target/arm: cpu64: some final cleanup on aarch64_cpu_finalize_features Claudio Fontana
2021-04-14 11:26 ` [RFC v13 78/80] XXX target/arm: experiment refactoring cpu "max" Claudio Fontana
2021-04-14 11:26 ` [RFC v13 79/80] target/arm: tcg: remove superfluous CONFIG_TCG check Claudio Fontana
2021-04-14 11:26 ` [RFC v13 80/80] target/arm: remove v7m stub function for !CONFIG_TCG Claudio Fontana
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