From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: [PULL v2 15/42] hw/opentitan: Update the interrupt layout
Date: Thu, 6 May 2021 09:22:45 +1000 [thread overview]
Message-ID: <20210505232312.4175486-16-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com>
Update the OpenTitan interrupt layout to match the latest OpenTitan
bitstreams. This involves changing the Ibex PLIC memory layout and the
UART interrupts.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
---
include/hw/riscv/opentitan.h | 16 ++++++++--------
hw/intc/ibex_plic.c | 20 ++++++++++----------
hw/riscv/opentitan.c | 8 ++++----
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index a5ea3a5e4e..aab9bc9245 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -82,14 +82,14 @@ enum {
};
enum {
- IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
- IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
- IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
- IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
- IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
- IBEX_UART_TX_EMPTY_IRQ = 0x23,
- IBEX_UART_RX_WATERMARK_IRQ = 0x22,
- IBEX_UART_TX_WATERMARK_IRQ = 0x21,
+ IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
+ IBEX_UART0_RX_TIMEOUT_IRQ = 7,
+ IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
+ IBEX_UART0_RX_FRAME_ERR_IRQ = 5,
+ IBEX_UART0_RX_OVERFLOW_IRQ = 4,
+ IBEX_UART0_TX_EMPTY_IRQ = 3,
+ IBEX_UART0_RX_WATERMARK_IRQ = 2,
+ IBEX_UART0_TX_WATERMARK_IRQ = 1,
};
#endif
diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
index c1b72fcab0..edf76e4f61 100644
--- a/hw/intc/ibex_plic.c
+++ b/hw/intc/ibex_plic.c
@@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int irq, int level)
static Property ibex_plic_properties[] = {
DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1),
- DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80),
+ DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176),
DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0),
- DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3),
+ DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6),
- DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c),
- DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3),
+ DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18),
+ DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6),
- DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18),
- DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80),
+ DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30),
+ DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177),
- DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200),
- DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3),
+ DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300),
+ DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6),
- DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c),
+ DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318),
- DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210),
+ DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index dc9dea117e..557d73726b 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
0, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_WATERMARK_IRQ));
+ IBEX_UART0_TX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
1, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_WATERMARK_IRQ));
+ IBEX_UART0_RX_WATERMARK_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
2, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_TX_EMPTY_IRQ));
+ IBEX_UART0_TX_EMPTY_IRQ));
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
3, qdev_get_gpio_in(DEVICE(&s->plic),
- IBEX_UART_RX_OVERFLOW_IRQ));
+ IBEX_UART0_RX_OVERFLOW_IRQ));
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
--
2.31.1
next prev parent reply other threads:[~2021-05-05 23:46 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 23:22 [PULL v2 00/42] riscv-to-apply queue Alistair Francis
2021-05-05 23:22 ` [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-05 23:22 ` [PULL v2 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-05 23:22 ` [PULL v2 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-05 23:22 ` [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-05 23:22 ` [PULL v2 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-05 23:22 ` [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-05 23:22 ` [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-05 23:22 ` [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-05 23:22 ` [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-05 23:22 ` [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-05 23:22 ` [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-05 23:22 ` [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-05 23:22 ` Alistair Francis [this message]
2021-05-05 23:22 ` [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-05 23:22 ` [PULL v2 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-05 23:22 ` [PULL v2 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-05 23:22 ` [PULL v2 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-05 23:22 ` [PULL v2 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-05 23:22 ` [PULL v2 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-05 23:22 ` [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-05 23:22 ` [PULL v2 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-05 23:22 ` [PULL v2 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-05 23:22 ` [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-05 23:22 ` [PULL v2 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-05 23:23 ` [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-05 23:23 ` [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-05 23:23 ` [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-11 8:29 ` [PULL v2 00/42] riscv-to-apply queue Peter Maydell
2021-05-11 10:17 ` Alistair Francis
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