From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: Hou Weiying <weiying_hou@outlook.com>,
qemu-devel@nongnu.org, Hongzheng-Li <Ethan.Lee.QNL@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
Myriad-Dreamin <camiyoru@gmail.com>
Subject: [PULL v2 23/42] target/riscv: Add ePMP CSR access functions
Date: Thu, 6 May 2021 09:22:53 +1000 [thread overview]
Message-ID: <20210505232312.4175486-24-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com>
From: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 270762cb2507fba6a9eeb99a774cf49f7da9cc32.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
- Rebase on master
- Fix build errors
- Fix some style issues
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu.h | 1 +
target/riscv/pmp.h | 14 ++++++++++++++
target/riscv/csr.c | 24 ++++++++++++++++++++++++
target/riscv/pmp.c | 34 ++++++++++++++++++++++++++++++++++
target/riscv/trace-events | 3 +++
5 files changed, 76 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 13a08b86f6..83b315e0b2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -230,6 +230,7 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
+ target_ulong mseccfg;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(uint32_t);
diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h
index b82a30f0d5..a9a0b363a7 100644
--- a/target/riscv/pmp.h
+++ b/target/riscv/pmp.h
@@ -36,6 +36,12 @@ typedef enum {
PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */
} pmp_am_t;
+typedef enum {
+ MSECCFG_MML = 1 << 0,
+ MSECCFG_MMWP = 1 << 1,
+ MSECCFG_RLB = 1 << 2
+} mseccfg_field_t;
+
typedef struct {
target_ulong addr_reg;
uint8_t cfg_reg;
@@ -55,6 +61,10 @@ typedef struct {
void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index,
target_ulong val);
target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index);
+
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val);
+target_ulong mseccfg_csr_read(CPURISCVState *env);
+
void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index,
target_ulong val);
target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index);
@@ -68,4 +78,8 @@ void pmp_update_rule_nums(CPURISCVState *env);
uint32_t pmp_get_num_rules(CPURISCVState *env);
int pmp_priv_to_page_prot(pmp_priv_t pmp_priv);
+#define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)
+#define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)
+#define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
+
#endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f0a74f0eb8..97ceff718f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -200,6 +200,15 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException epmp(CPURISCVState *env, int csrno)
+{
+ if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
/* User Floating-Point CSRs */
@@ -1343,6 +1352,20 @@ static RISCVException write_mtinst(CPURISCVState *env, int csrno,
}
/* Physical Memory Protection */
+static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = mseccfg_csr_read(env);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ mseccfg_csr_write(env, val);
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -1581,6 +1604,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MTINST] = { "mtinst", hmode, read_mtinst, write_mtinst },
/* Physical Memory Protection */
+ [CSR_MSECCFG] = { "mseccfg", epmp, read_mseccfg, write_mseccfg },
[CSR_PMPCFG0] = { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG1] = { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg },
[CSR_PMPCFG2] = { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg },
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index a3b253bb15..e35988eec2 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -419,6 +419,40 @@ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index)
return val;
}
+/*
+ * Handle a write to a mseccfg CSR
+ */
+void mseccfg_csr_write(CPURISCVState *env, target_ulong val)
+{
+ int i;
+
+ trace_mseccfg_csr_write(env->mhartid, val);
+
+ /* RLB cannot be enabled if it's already 0 and if any regions are locked */
+ if (!MSECCFG_RLB_ISSET(env)) {
+ for (i = 0; i < MAX_RISCV_PMPS; i++) {
+ if (pmp_is_locked(env, i)) {
+ val &= ~MSECCFG_RLB;
+ break;
+ }
+ }
+ }
+
+ /* Sticky bits */
+ val |= (env->mseccfg & (MSECCFG_MMWP | MSECCFG_MML));
+
+ env->mseccfg = val;
+}
+
+/*
+ * Handle a read from a mseccfg CSR
+ */
+target_ulong mseccfg_csr_read(CPURISCVState *env)
+{
+ trace_mseccfg_csr_read(env->mhartid, env->mseccfg);
+ return env->mseccfg;
+}
+
/*
* Calculate the TLB size if the start address or the end address of
* PMP entry is presented in thie TLB page.
diff --git a/target/riscv/trace-events b/target/riscv/trace-events
index b7e371ee97..49ec4d3b7d 100644
--- a/target/riscv/trace-events
+++ b/target/riscv/trace-events
@@ -6,3 +6,6 @@ pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRI
pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64
pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64
+
+mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
+mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
--
2.31.1
next prev parent reply other threads:[~2021-05-05 23:35 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 23:22 [PULL v2 00/42] riscv-to-apply queue Alistair Francis
2021-05-05 23:22 ` [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-05 23:22 ` [PULL v2 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-05 23:22 ` [PULL v2 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-05 23:22 ` [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-05 23:22 ` [PULL v2 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-05 23:22 ` [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-05 23:22 ` [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-05 23:22 ` [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-05 23:22 ` [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-05 23:22 ` [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-05 23:22 ` [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-05 23:22 ` [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-05 23:22 ` [PULL v2 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-05 23:22 ` [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-05 23:22 ` [PULL v2 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-05 23:22 ` [PULL v2 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-05 23:22 ` [PULL v2 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-05 23:22 ` [PULL v2 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-05 23:22 ` Alistair Francis [this message]
2021-05-05 23:22 ` [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-05 23:22 ` [PULL v2 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-05 23:22 ` [PULL v2 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-05 23:22 ` [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-05 23:22 ` [PULL v2 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-05 23:23 ` [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-05 23:23 ` [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-05 23:23 ` [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-11 8:29 ` [PULL v2 00/42] riscv-to-apply queue Peter Maydell
2021-05-11 10:17 ` Alistair Francis
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