From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: Hou Weiying <weiying_hou@outlook.com>,
qemu-devel@nongnu.org, Hongzheng-Li <Ethan.Lee.QNL@gmail.com>,
Alistair Francis <alistair.francis@wdc.com>,
alistair23@gmail.com, Bin Meng <bmeng.cn@gmail.com>,
Myriad-Dreamin <camiyoru@gmail.com>
Subject: [PULL v2 21/42] target/riscv: Define ePMP mseccfg
Date: Thu, 6 May 2021 09:22:51 +1000 [thread overview]
Message-ID: <20210505232312.4175486-22-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210505232312.4175486-1-alistair.francis@wdc.com>
From: Hou Weiying <weiying_hou@outlook.com>
Use address 0x390 and 0x391 for the ePMP CSRs.
Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 63245b559f477a9ce6d4f930136d2d7fd7f99c78.1618812899.git.alistair.francis@wdc.com
[ Changes by AF:
- Tidy up commit message
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
target/riscv/cpu_bits.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8549d77b4f..24d89939a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -220,6 +220,9 @@
#define CSR_MTINST 0x34a
#define CSR_MTVAL2 0x34b
+/* Enhanced Physical Memory Protection (ePMP) */
+#define CSR_MSECCFG 0x390
+#define CSR_MSECCFGH 0x391
/* Physical Memory Protection */
#define CSR_PMPCFG0 0x3a0
#define CSR_PMPCFG1 0x3a1
--
2.31.1
next prev parent reply other threads:[~2021-05-05 23:35 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-05 23:22 [PULL v2 00/42] riscv-to-apply queue Alistair Francis
2021-05-05 23:22 ` [PULL v2 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-05 23:22 ` [PULL v2 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-05 23:22 ` [PULL v2 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-05 23:22 ` [PULL v2 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-05 23:22 ` [PULL v2 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-05 23:22 ` [PULL v2 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-05 23:22 ` [PULL v2 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-05 23:22 ` [PULL v2 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-05 23:22 ` [PULL v2 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-05 23:22 ` [PULL v2 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-05 23:22 ` [PULL v2 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-05 23:22 ` [PULL v2 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-05 23:22 ` [PULL v2 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-05 23:22 ` [PULL v2 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-05 23:22 ` [PULL v2 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-05 23:22 ` [PULL v2 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-05 23:22 ` [PULL v2 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-05 23:22 ` Alistair Francis [this message]
2021-05-05 23:22 ` [PULL v2 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-05 23:22 ` [PULL v2 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-05 23:22 ` [PULL v2 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-05 23:22 ` [PULL v2 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-05 23:22 ` [PULL v2 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-05 23:22 ` [PULL v2 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-05 23:22 ` [PULL v2 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-05 23:22 ` [PULL v2 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-05 23:23 ` [PULL v2 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-05 23:23 ` [PULL v2 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-05 23:23 ` [PULL v2 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-05 23:23 ` [PULL v2 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-05 23:23 ` [PULL v2 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-11 8:29 ` [PULL v2 00/42] riscv-to-apply queue Peter Maydell
2021-05-11 10:17 ` Alistair Francis
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