From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, Jade Fink <qemu@jade.fyi>
Subject: [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context
Date: Tue, 11 May 2021 20:19:26 +1000 [thread overview]
Message-ID: <20210511101951.165287-18-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210511101951.165287-1-alistair.francis@wdc.com>
From: Jade Fink <qemu@jade.fyi>
Previously the qemu monitor and gdbstub looked at SUM and refused to
perform accesses to user memory if it is off, which was an impediment to
debugging.
Signed-off-by: Jade Fink <qemu@jade.fyi>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210406113109.1031033-1-qemu@jade.fyi
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 99cc388db9..659ca8a173 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -342,12 +342,14 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
* @first_stage: Are we in first stage translation?
* Second stage is used for hypervisor guest translation
* @two_stage: Are we going to perform two stage translation
+ * @is_debug: Is this access from a debugger or the monitor?
*/
static int get_physical_address(CPURISCVState *env, hwaddr *physical,
int *prot, target_ulong addr,
target_ulong *fault_pte_addr,
int access_type, int mmu_idx,
- bool first_stage, bool two_stage)
+ bool first_stage, bool two_stage,
+ bool is_debug)
{
/* NOTE: the env->pc value visible here will not be
* correct, but the value visible to the exception handler
@@ -416,7 +418,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
widened = 2;
}
/* status.SUM will be ignored if execute on background */
- sum = get_field(env->mstatus, MSTATUS_SUM) || use_background;
+ sum = get_field(env->mstatus, MSTATUS_SUM) || use_background || is_debug;
switch (vm) {
case VM_1_10_SV32:
levels = 2; ptidxbits = 10; ptesize = 4; break;
@@ -475,7 +477,8 @@ restart:
/* Do the second stage translation on the base PTE address. */
int vbase_ret = get_physical_address(env, &vbase, &vbase_prot,
base, NULL, MMU_DATA_LOAD,
- mmu_idx, false, true);
+ mmu_idx, false, true,
+ is_debug);
if (vbase_ret != TRANSLATE_SUCCESS) {
if (fault_pte_addr) {
@@ -666,13 +669,13 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int mmu_idx = cpu_mmu_index(&cpu->env, false);
if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx,
- true, riscv_cpu_virt_enabled(env))) {
+ true, riscv_cpu_virt_enabled(env), true)) {
return -1;
}
if (riscv_cpu_virt_enabled(env)) {
if (get_physical_address(env, &phys_addr, &prot, phys_addr, NULL,
- 0, mmu_idx, false, true)) {
+ 0, mmu_idx, false, true, true)) {
return -1;
}
}
@@ -768,7 +771,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
/* Two stage lookup */
ret = get_physical_address(env, &pa, &prot, address,
&env->guest_phys_fault_addr, access_type,
- mmu_idx, true, true);
+ mmu_idx, true, true, false);
/*
* A G-stage exception may be triggered during two state lookup.
@@ -790,7 +793,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
im_address = pa;
ret = get_physical_address(env, &pa, &prot2, im_address, NULL,
- access_type, mmu_idx, false, true);
+ access_type, mmu_idx, false, true,
+ false);
qemu_log_mask(CPU_LOG_MMU,
"%s 2nd-stage address=%" VADDR_PRIx " ret %d physical "
@@ -825,7 +829,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} else {
/* Single stage lookup */
ret = get_physical_address(env, &pa, &prot, address, NULL,
- access_type, mmu_idx, true, false);
+ access_type, mmu_idx, true, false, false);
qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical "
--
2.31.1
next prev parent reply other threads:[~2021-05-11 10:41 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 10:19 [PULL v3 00/42] riscv-to-apply queue Alistair Francis
2021-05-11 10:19 ` [PULL v3 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-11 10:19 ` [PULL v3 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-11 10:19 ` [PULL v3 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-11 10:19 ` [PULL v3 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-11 10:19 ` [PULL v3 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-11 10:19 ` [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-11 10:19 ` [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-11 10:19 ` [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-11 10:19 ` [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-11 10:19 ` [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-11 10:19 ` [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-11 10:19 ` [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-11 10:19 ` [PULL v3 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-11 10:19 ` [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-11 10:19 ` Alistair Francis [this message]
2021-05-11 10:19 ` [PULL v3 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-11 10:19 ` [PULL v3 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-11 10:19 ` [PULL v3 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-11 10:19 ` [PULL v3 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-11 10:19 ` [PULL v3 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-11 10:19 ` [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-20 13:51 ` Peter Maydell
2021-05-20 22:38 ` Alistair Francis
2021-05-11 10:19 ` [PULL v3 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-11 10:19 ` [PULL v3 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-11 10:19 ` [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-11 10:19 ` [PULL v3 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-11 10:19 ` [PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-11 10:19 ` [PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-11 10:19 ` [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-20 13:55 ` Peter Maydell
2021-05-20 22:55 ` Alistair Francis
2021-05-21 2:07 ` LIU Zhiwei
2021-05-25 21:47 ` Alistair Francis
2021-05-11 10:19 ` [PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-12 18:46 ` [PULL v3 00/42] riscv-to-apply queue Peter Maydell
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