From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: [PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro
Date: Tue, 11 May 2021 20:19:46 +1000 [thread overview]
Message-ID: <20210511101951.165287-38-alistair.francis@wdc.com> (raw)
In-Reply-To: <20210511101951.165287-1-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 6b701769d6621f45ba1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
---
target/riscv/cpu_bits.h | 11 -----------
target/riscv/cpu_helper.c | 32 ++++++++++++++++++++++++--------
target/riscv/csr.c | 19 +++++++++++++++----
target/riscv/monitor.c | 22 +++++++++++++++++-----
4 files changed, 56 insertions(+), 28 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 6e30b312f0..d98f3bc8bc 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -432,17 +432,6 @@
#define SATP64_ASID 0x0FFFF00000000000ULL
#define SATP64_PPN 0x00000FFFFFFFFFFFULL
-#if defined(TARGET_RISCV32)
-#define SATP_MODE SATP32_MODE
-#define SATP_ASID SATP32_ASID
-#define SATP_PPN SATP32_PPN
-#endif
-#if defined(TARGET_RISCV64)
-#define SATP_MODE SATP64_MODE
-#define SATP_ASID SATP64_ASID
-#define SATP_PPN SATP64_PPN
-#endif
-
/* VM modes (mstatus.vm) privileged ISA 1.9.1 */
#define VM_1_09_MBARE 0
#define VM_1_09_MBB 1
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index d9defbdd34..968cb8046f 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -405,11 +405,21 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
if (first_stage == true) {
if (use_background) {
- base = (hwaddr)get_field(env->vsatp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->vsatp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->vsatp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->vsatp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->vsatp, SATP64_MODE);
+ }
} else {
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
- vm = get_field(env->satp, SATP_MODE);
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
}
widened = 0;
} else {
@@ -624,14 +634,20 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
{
CPUState *cs = env_cpu(env);
int page_fault_exceptions, vm;
+ uint64_t stap_mode;
+
+ if (riscv_cpu_is_32bit(env)) {
+ stap_mode = SATP32_MODE;
+ } else {
+ stap_mode = SATP64_MODE;
+ }
if (first_stage) {
- vm = get_field(env->satp, SATP_MODE);
- } else if (riscv_cpu_is_32bit(env)) {
- vm = get_field(env->hgatp, SATP32_MODE);
+ vm = get_field(env->satp, stap_mode);
} else {
- vm = get_field(env->hgatp, SATP64_MODE);
+ vm = get_field(env->hgatp, stap_mode);
}
+
page_fault_exceptions = vm != VM_1_10_MBARE && !pmp_violation;
switch (access_type) {
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e955753441..fe5628fea6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -997,16 +997,27 @@ static RISCVException read_satp(CPURISCVState *env, int csrno,
static RISCVException write_satp(CPURISCVState *env, int csrno,
target_ulong val)
{
+ int vm, mask, asid;
+
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
return RISCV_EXCP_NONE;
}
- if (validate_vm(env, get_field(val, SATP_MODE)) &&
- ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
- {
+
+ if (riscv_cpu_is_32bit(env)) {
+ vm = validate_vm(env, get_field(val, SATP32_MODE));
+ mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
+ asid = (val ^ env->satp) & SATP32_ASID;
+ } else {
+ vm = validate_vm(env, get_field(val, SATP64_MODE));
+ mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
+ asid = (val ^ env->satp) & SATP64_ASID;
+ }
+
+ if (vm && mask) {
if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
- if ((val ^ env->satp) & SATP_ASID) {
+ if (asid) {
tlb_flush(env_cpu(env));
}
env->satp = val;
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index e51188f919..f7e6ea72b3 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -150,9 +150,14 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
target_ulong last_size;
int last_attr;
- base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT;
+ if (riscv_cpu_is_32bit(env)) {
+ base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP32_MODE);
+ } else {
+ base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
+ vm = get_field(env->satp, SATP64_MODE);
+ }
- vm = get_field(env->satp, SATP_MODE);
switch (vm) {
case VM_1_10_SV32:
levels = 2;
@@ -215,9 +220,16 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
return;
}
- if (!(env->satp & SATP_MODE)) {
- monitor_printf(mon, "No translation or protection\n");
- return;
+ if (riscv_cpu_is_32bit(env)) {
+ if (!(env->satp & SATP32_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
+ } else {
+ if (!(env->satp & SATP64_MODE)) {
+ monitor_printf(mon, "No translation or protection\n");
+ return;
+ }
}
mem_info_svxx(mon, env);
--
2.31.1
next prev parent reply other threads:[~2021-05-11 10:49 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 10:19 [PULL v3 00/42] riscv-to-apply queue Alistair Francis
2021-05-11 10:19 ` [PULL v3 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-11 10:19 ` [PULL v3 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-11 10:19 ` [PULL v3 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-11 10:19 ` [PULL v3 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-11 10:19 ` [PULL v3 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-11 10:19 ` [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-11 10:19 ` [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-11 10:19 ` [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-11 10:19 ` [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-11 10:19 ` [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-11 10:19 ` [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-11 10:19 ` [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-11 10:19 ` [PULL v3 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-11 10:19 ` [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-11 10:19 ` [PULL v3 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-11 10:19 ` [PULL v3 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-11 10:19 ` [PULL v3 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-11 10:19 ` [PULL v3 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-11 10:19 ` [PULL v3 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-11 10:19 ` [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-20 13:51 ` Peter Maydell
2021-05-20 22:38 ` Alistair Francis
2021-05-11 10:19 ` [PULL v3 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-11 10:19 ` [PULL v3 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-11 10:19 ` [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-11 10:19 ` [PULL v3 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-11 10:19 ` [PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-11 10:19 ` [PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-11 10:19 ` [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-20 13:55 ` Peter Maydell
2021-05-20 22:55 ` Alistair Francis
2021-05-21 2:07 ` LIU Zhiwei
2021-05-25 21:47 ` Alistair Francis
2021-05-11 10:19 ` Alistair Francis [this message]
2021-05-11 10:19 ` [PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-12 18:46 ` [PULL v3 00/42] riscv-to-apply queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210511101951.165287-38-alistair.francis@wdc.com \
--to=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).