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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len
Date: Tue, 27 Jul 2021 11:47:57 +0100	[thread overview]
Message-ID: <20210727104801.29728-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210727104801.29728-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Currently, our only caller is sve_zcr_len_for_el, which has
already masked the length extracted from ZCR_ELx, so the
masking done here is a nop.  But we will shortly have uses
from other locations, where the length will be unmasked.

Saturate the length to ARM_MAX_VQ instead of truncating to
the low 4 bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20210723203344.968563-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 0c07ca98376..8c1d8dbce36 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6461,7 +6461,9 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
 {
     uint32_t end_len;
 
-    end_len = start_len &= 0xf;
+    start_len = MIN(start_len, ARM_MAX_VQ - 1);
+    end_len = start_len;
+
     if (!test_bit(start_len, cpu->sve_vq_map)) {
         end_len = find_last_bit(cpu->sve_vq_map, start_len);
         assert(end_len < start_len);
-- 
2.20.1



  parent reply	other threads:[~2021-07-27 10:57 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-27 10:47 [PULL 00/14] target-arm queue Peter Maydell
2021-07-27 10:47 ` [PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid Peter Maydell
2021-07-27 10:47 ` [PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option Peter Maydell
2021-07-27 10:47 ` [PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero Peter Maydell
2021-07-27 10:47 ` [PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken() Peter Maydell
2021-07-27 10:47 ` [PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest Peter Maydell
2021-07-27 10:47 ` [PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts Peter Maydell
2021-07-27 10:47 ` [PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING Peter Maydell
2021-07-27 10:47 ` [PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS Peter Maydell
2021-07-27 10:47 ` [PULL 09/14] docs: Update path that mentions deprecated.rst Peter Maydell
2021-07-27 10:47 ` Peter Maydell [this message]
2021-07-27 10:47 ` [PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len Peter Maydell
2021-07-27 10:47 ` [PULL 12/14] target/arm: Add sve-default-vector-length cpu property Peter Maydell
2021-07-27 10:48 ` [PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix Peter Maydell
2021-07-27 10:48 ` [PULL 14/14] hw: aspeed_gpio: Fix memory size Peter Maydell
2021-07-27 17:05 ` [PULL 00/14] target-arm queue Peter Maydell

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