From: Peter Maydell <peter.maydell@linaro.org>
To: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PULL 00/14] target-arm queue
Date: Tue, 27 Jul 2021 18:05:47 +0100 [thread overview]
Message-ID: <CAFEAcA8=qgwVZ7vVK_jbwGdR6DOn30Y2avbpp0GUNcib2E9wVA@mail.gmail.com> (raw)
In-Reply-To: <20210727104801.29728-1-peter.maydell@linaro.org>
On Tue, 27 Jul 2021 at 11:48, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> arm pullreq for rc1. All minor bugfixes, except for the sve-default-vector-length
> patches, which are somewhere between a bugfix and a new feature.
>
> thanks
> -- PMM
>
> The following changes since commit c08ccd1b53f488ac86c1f65cf7623dc91acc249a:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210726' into staging (2021-07-27 08:35:01 +0100)
>
> are available in the Git repository at:
>
> https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210727
>
> for you to fetch changes up to e229a179a503f2aee43a76888cf12fbdfe8a3749:
>
> hw: aspeed_gpio: Fix memory size (2021-07-27 11:00:00 +0100)
>
> ----------------------------------------------------------------
> target-arm queue:
> * hw/arm/smmuv3: Check 31st bit to see if CD is valid
> * qemu-options.hx: Fix formatting of -machine memory-backend option
> * hw: aspeed_gpio: Fix memory size
> * hw/arm/nseries: Display hexadecimal value with '0x' prefix
> * Add sve-default-vector-length cpu property
> * docs: Update path that mentions deprecated.rst
> * hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
> * hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING
> * hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
> * target/arm: Report M-profile alignment faults correctly to the guest
> * target/arm: Add missing 'return's after calling v7m_exception_taken()
> * target/arm: Enforce that M-profile SP low 2 bits are always zero
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1
for any user-visible changes.
-- PMM
next prev parent reply other threads:[~2021-07-27 17:11 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-27 10:47 [PULL 00/14] target-arm queue Peter Maydell
2021-07-27 10:47 ` [PULL 01/14] hw/arm/smmuv3: Check 31st bit to see if CD is valid Peter Maydell
2021-07-27 10:47 ` [PULL 02/14] qemu-options.hx: Fix formatting of -machine memory-backend option Peter Maydell
2021-07-27 10:47 ` [PULL 03/14] target/arm: Enforce that M-profile SP low 2 bits are always zero Peter Maydell
2021-07-27 10:47 ` [PULL 04/14] target/arm: Add missing 'return's after calling v7m_exception_taken() Peter Maydell
2021-07-27 10:47 ` [PULL 05/14] target/arm: Report M-profile alignment faults correctly to the guest Peter Maydell
2021-07-27 10:47 ` [PULL 06/14] hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts Peter Maydell
2021-07-27 10:47 ` [PULL 07/14] hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDING Peter Maydell
2021-07-27 10:47 ` [PULL 08/14] hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS Peter Maydell
2021-07-27 10:47 ` [PULL 09/14] docs: Update path that mentions deprecated.rst Peter Maydell
2021-07-27 10:47 ` [PULL 10/14] target/arm: Correctly bound length in sve_zcr_get_valid_len Peter Maydell
2021-07-27 10:47 ` [PULL 11/14] target/arm: Export aarch64_sve_zcr_get_valid_len Peter Maydell
2021-07-27 10:47 ` [PULL 12/14] target/arm: Add sve-default-vector-length cpu property Peter Maydell
2021-07-27 10:48 ` [PULL 13/14] hw/arm/nseries: Display hexadecimal value with '0x' prefix Peter Maydell
2021-07-27 10:48 ` [PULL 14/14] hw: aspeed_gpio: Fix memory size Peter Maydell
2021-07-27 17:05 ` Peter Maydell [this message]
2024-03-08 15:50 [PULL 00/14] target-arm queue Peter Maydell
2024-03-09 14:58 ` Peter Maydell
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