From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org
Subject: [PATCH v4 00/21] target/riscv: Use tcg_constant_*
Date: Fri, 20 Aug 2021 07:42:36 -1000 [thread overview]
Message-ID: <20210820174257.548286-1-richard.henderson@linaro.org> (raw)
Replace use of tcg_const_*, which makes a copy into a temp which must
be freed, with direct use of the constant. Reorg handling of $zero,
with different accessors for source and destination. Reorg handling
of csrs, passing the actual write_mask instead of a regno. Use more
helpers for RVH expansion.
Patches lacking review:
02-tests-tcg-riscv64-Add-test-for-division.patch
03-target-riscv-Clean-up-division-helpers.patch
11-target-riscv-Add-DisasExtend-to-gen_unary.patch
17-target-riscv-Use-gen_shift_imm_fn-for-slli_uw.patch
21-target-riscv-Use-get-dest-_gpr-for-RVV.patch
Changes for v4:
* Add a test for division, primarily checking the edge cases.
* Dropped the greviw patch, since grev has been dropped from Zbb 1.0.0.
Changes for v3:
* Fix an introduced remainder bug (bin meng),
and remove one extra movcond from rem/remu.
* Do not zero DisasContext on allocation (bin meng).
Changes for v2:
* Retain the requirement to call gen_set_gpr.
* Add DisasExtend as an argument to get_gpr, and ctx->w as a member
of DisasContext. This should help in implementing UXL, where we
should be able to set ctx->w for all insns, but there is certainly
more required for that.
r~
Richard Henderson (21):
target/riscv: Use tcg_constant_*
tests/tcg/riscv64: Add test for division
target/riscv: Clean up division helpers
target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr
target/riscv: Introduce DisasExtend and new helpers
target/riscv: Add DisasExtend to gen_arith*
target/riscv: Remove gen_arith_div*
target/riscv: Use gen_arith for mulh and mulhu
target/riscv: Move gen_* helpers for RVM
target/riscv: Move gen_* helpers for RVB
target/riscv: Add DisasExtend to gen_unary
target/riscv: Use DisasExtend in shift operations
target/riscv: Use get_gpr in branches
target/riscv: Use {get,dest}_gpr for integer load/store
target/riscv: Reorg csr instructions
target/riscv: Use {get,dest}_gpr for RVA
target/riscv: Use gen_shift_imm_fn for slli_uw
target/riscv: Use {get,dest}_gpr for RVF
target/riscv: Use {get,dest}_gpr for RVD
target/riscv: Tidy trans_rvh.c.inc
target/riscv: Use {get,dest}_gpr for RVV
target/riscv/helper.h | 6 +-
target/riscv/insn32.decode | 1 +
target/riscv/op_helper.c | 18 +-
target/riscv/translate.c | 701 ++++++------------------
tests/tcg/riscv64/test-div.c | 58 ++
target/riscv/insn_trans/trans_rva.c.inc | 51 +-
target/riscv/insn_trans/trans_rvb.c.inc | 370 ++++++++++---
target/riscv/insn_trans/trans_rvd.c.inc | 127 +++--
target/riscv/insn_trans/trans_rvf.c.inc | 149 +++--
target/riscv/insn_trans/trans_rvh.c.inc | 266 ++-------
target/riscv/insn_trans/trans_rvi.c.inc | 360 ++++++------
target/riscv/insn_trans/trans_rvm.c.inc | 191 +++++--
target/riscv/insn_trans/trans_rvv.c.inc | 151 ++---
tests/tcg/riscv64/Makefile.target | 5 +
14 files changed, 1125 insertions(+), 1329 deletions(-)
create mode 100644 tests/tcg/riscv64/test-div.c
create mode 100644 tests/tcg/riscv64/Makefile.target
--
2.25.1
next reply other threads:[~2021-08-20 17:45 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 17:42 Richard Henderson [this message]
2021-08-20 17:42 ` [PATCH v4 01/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 02/21] tests/tcg/riscv64: Add test for division Richard Henderson
2021-08-23 3:18 ` Bin Meng
2021-08-23 6:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 03/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-23 4:07 ` Bin Meng
2021-08-23 6:09 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 04/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-20 17:42 ` [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-20 17:42 ` [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 07/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-20 17:42 ` [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-20 17:42 ` [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-23 6:13 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-23 6:15 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-23 6:18 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-23 6:19 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-23 7:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-23 4:54 ` Bin Meng
2021-08-23 19:54 ` Richard Henderson
2021-08-20 17:42 ` [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA Richard Henderson
2021-08-20 17:42 ` [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-20 17:42 ` [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-20 17:42 ` [PATCH v4 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-20 17:42 ` [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-20 17:42 ` [PATCH v4 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-30 10:12 ` [PATCH v4 00/21] target/riscv: Use tcg_constant_* Alistair Francis
2021-08-30 15:26 ` Richard Henderson
2021-08-31 0:20 ` Alistair Francis
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