From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, bin.meng@windriver.com,
qemu-riscv@nongnu.org, Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v4 16/21] target/riscv: Use {get,dest}_gpr for RVA
Date: Fri, 20 Aug 2021 07:42:52 -1000 [thread overview]
Message-ID: <20210820174257.548286-17-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210820174257.548286-1-richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rva.c.inc | 47 ++++++++++---------------
1 file changed, 19 insertions(+), 28 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc
index 3cc3c3b073..6ea07d89b0 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -18,11 +18,10 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
- TCGv src1 = tcg_temp_new();
- /* Put addr in load_res, data in load_val. */
- gen_get_gpr(ctx, src1, a->rs1);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
@@ -30,33 +29,33 @@ static inline bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
+
+ /* Put addr in load_res, data in load_val. */
tcg_gen_mov_tl(load_res, src1);
gen_set_gpr(ctx, a->rd, load_val);
- tcg_temp_free(src1);
return true;
}
-static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
+static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
{
- TCGv src1 = tcg_temp_new();
- TCGv src2 = tcg_temp_new();
- TCGv dat = tcg_temp_new();
+ TCGv dest, src1, src2;
TCGLabel *l1 = gen_new_label();
TCGLabel *l2 = gen_new_label();
- gen_get_gpr(ctx, src1, a->rs1);
+ src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
- gen_get_gpr(ctx, src2, a->rs2);
/*
* Note that the TCG atomic primitives are SC,
* so we can ignore AQ/RL along this path.
*/
- tcg_gen_atomic_cmpxchg_tl(src1, load_res, load_val, src2,
+ dest = dest_gpr(ctx, a->rd);
+ src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ tcg_gen_atomic_cmpxchg_tl(dest, load_res, load_val, src2,
ctx->mem_idx, mop);
- tcg_gen_setcond_tl(TCG_COND_NE, dat, src1, load_val);
- gen_set_gpr(ctx, a->rd, dat);
+ tcg_gen_setcond_tl(TCG_COND_NE, dest, dest, load_val);
+ gen_set_gpr(ctx, a->rd, dest);
tcg_gen_br(l2);
gen_set_label(l1);
@@ -65,8 +64,7 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
* provide the memory barrier implied by AQ/RL.
*/
tcg_gen_mb(TCG_MO_ALL + a->aq * TCG_BAR_LDAQ + a->rl * TCG_BAR_STRL);
- tcg_gen_movi_tl(dat, 1);
- gen_set_gpr(ctx, a->rd, dat);
+ gen_set_gpr(ctx, a->rd, tcg_constant_tl(1));
gen_set_label(l2);
/*
@@ -75,9 +73,6 @@ static inline bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
*/
tcg_gen_movi_tl(load_res, -1);
- tcg_temp_free(dat);
- tcg_temp_free(src1);
- tcg_temp_free(src2);
return true;
}
@@ -85,17 +80,13 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp),
MemOp mop)
{
- TCGv src1 = tcg_temp_new();
- TCGv src2 = tcg_temp_new();
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+ TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
- gen_get_gpr(ctx, src1, a->rs1);
- gen_get_gpr(ctx, src2, a->rs2);
+ func(dest, src1, src2, ctx->mem_idx, mop);
- (*func)(src2, src1, src2, ctx->mem_idx, mop);
-
- gen_set_gpr(ctx, a->rd, src2);
- tcg_temp_free(src1);
- tcg_temp_free(src2);
+ gen_set_gpr(ctx, a->rd, dest);
return true;
}
--
2.25.1
next prev parent reply other threads:[~2021-08-20 17:55 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-20 17:42 [PATCH v4 00/21] target/riscv: Use tcg_constant_* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 01/21] " Richard Henderson
2021-08-20 17:42 ` [PATCH v4 02/21] tests/tcg/riscv64: Add test for division Richard Henderson
2021-08-23 3:18 ` Bin Meng
2021-08-23 6:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 03/21] target/riscv: Clean up division helpers Richard Henderson
2021-08-23 4:07 ` Bin Meng
2021-08-23 6:09 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 04/21] target/riscv: Add DisasContext to gen_get_gpr, gen_set_gpr Richard Henderson
2021-08-20 17:42 ` [PATCH v4 05/21] target/riscv: Introduce DisasExtend and new helpers Richard Henderson
2021-08-20 17:42 ` [PATCH v4 06/21] target/riscv: Add DisasExtend to gen_arith* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 07/21] target/riscv: Remove gen_arith_div* Richard Henderson
2021-08-20 17:42 ` [PATCH v4 08/21] target/riscv: Use gen_arith for mulh and mulhu Richard Henderson
2021-08-20 17:42 ` [PATCH v4 09/21] target/riscv: Move gen_* helpers for RVM Richard Henderson
2021-08-20 17:42 ` [PATCH v4 10/21] target/riscv: Move gen_* helpers for RVB Richard Henderson
2021-08-23 6:13 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 11/21] target/riscv: Add DisasExtend to gen_unary Richard Henderson
2021-08-23 6:15 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 12/21] target/riscv: Use DisasExtend in shift operations Richard Henderson
2021-08-23 6:18 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 13/21] target/riscv: Use get_gpr in branches Richard Henderson
2021-08-23 6:19 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 14/21] target/riscv: Use {get, dest}_gpr for integer load/store Richard Henderson
2021-08-23 7:04 ` Alistair Francis
2021-08-20 17:42 ` [PATCH v4 15/21] target/riscv: Reorg csr instructions Richard Henderson
2021-08-23 4:54 ` Bin Meng
2021-08-23 19:54 ` Richard Henderson
2021-08-20 17:42 ` Richard Henderson [this message]
2021-08-20 17:42 ` [PATCH v4 17/21] target/riscv: Use gen_shift_imm_fn for slli_uw Richard Henderson
2021-08-20 17:42 ` [PATCH v4 18/21] target/riscv: Use {get,dest}_gpr for RVF Richard Henderson
2021-08-20 17:42 ` [PATCH v4 19/21] target/riscv: Use {get,dest}_gpr for RVD Richard Henderson
2021-08-20 17:42 ` [PATCH v4 20/21] target/riscv: Tidy trans_rvh.c.inc Richard Henderson
2021-08-20 17:42 ` [PATCH v4 21/21] target/riscv: Use {get,dest}_gpr for RVV Richard Henderson
2021-08-30 10:12 ` [PATCH v4 00/21] target/riscv: Use tcg_constant_* Alistair Francis
2021-08-30 15:26 ` Richard Henderson
2021-08-31 0:20 ` Alistair Francis
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