From: frank.chang@sifive.com
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Frank Chang <frank.chang@sifive.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL
Date: Fri, 15 Oct 2021 15:45:14 +0800 [thread overview]
Message-ID: <20211015074627.3957162-14-frank.chang@sifive.com> (raw)
In-Reply-To: <20211015074627.3957162-1-frank.chang@sifive.com>
From: Frank Chang <frank.chang@sifive.com>
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Also rearrange rvv bits in TB_FLAGS to skip MSTATUS_VS (0x600)
and MSTATUS_FS (0x6000) bits.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 22 ++++++++++++----------
target/riscv/translate.c | 16 ++++++++++++++--
target/riscv/vector_helper.c | 16 ++++++++++++++--
3 files changed, 40 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fb41c1cea7c..1bd9b4123da 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -103,10 +103,10 @@ typedef struct CPURISCVState CPURISCVState;
#define RV_VLEN_MAX 256
-FIELD(VTYPE, VLMUL, 0, 2)
-FIELD(VTYPE, VSEW, 2, 3)
-FIELD(VTYPE, VEDIV, 5, 2)
-FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
+FIELD(VTYPE, VLMUL, 0, 3)
+FIELD(VTYPE, VSEW, 3, 3)
+FIELD(VTYPE, VEDIV, 8, 2)
+FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)
FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
struct CPURISCVState {
@@ -391,14 +391,16 @@ typedef RISCVCPU ArchCPU;
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, MEM_IDX, 0, 3)
-FIELD(TB_FLAGS, VL_EQ_VLMAX, 3, 1)
-FIELD(TB_FLAGS, LMUL, 4, 2)
+FIELD(TB_FLAGS, LMUL, 3, 3)
FIELD(TB_FLAGS, SEW, 6, 3)
-FIELD(TB_FLAGS, VILL, 9, 1)
+/* Skip MSTATUS_VS (0x600) bits */
+FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1)
+FIELD(TB_FLAGS, VILL, 12, 1)
+/* Skip MSTATUS_FS (0x6000) bits */
/* Is a Hypervisor instruction load/store allowed? */
-FIELD(TB_FLAGS, HLSX, 10, 1)
-FIELD(TB_FLAGS, MSTATUS_HS_FS, 11, 2)
-FIELD(TB_FLAGS, MSTATUS_HS_VS, 13, 2)
+FIELD(TB_FLAGS, HLSX, 15, 1)
+FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2)
+FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2)
bool riscv_cpu_is_32bit(CPURISCVState *env);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 174ef0564e6..6a3f105d431 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -76,7 +76,19 @@ typedef struct DisasContext {
bool hlsx;
/* vector extension */
bool vill;
- uint8_t lmul;
+ /*
+ * Encode LMUL to lmul as follows:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ */
+ int8_t lmul;
uint8_t sew;
uint16_t vlen;
bool vl_eq_vlmax;
@@ -606,7 +618,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
- ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL);
+ ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
ctx->cs = cs;
ctx->w = false;
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ac6c7298bc0..866bfb35714 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -86,9 +86,21 @@ static inline uint32_t vext_vm(uint32_t desc)
return FIELD_EX32(simd_data(desc), VDATA, VM);
}
-static inline uint32_t vext_lmul(uint32_t desc)
+/*
+ * Encode LMUL to lmul as following:
+ * LMUL vlmul lmul
+ * 1 000 0
+ * 2 001 1
+ * 4 010 2
+ * 8 011 3
+ * - 100 -
+ * 1/8 101 -3
+ * 1/4 110 -2
+ * 1/2 111 -1
+ */
+static inline int32_t vext_lmul(uint32_t desc)
{
- return FIELD_EX32(simd_data(desc), VDATA, LMUL);
+ return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3);
}
static uint32_t vext_wd(uint32_t desc)
--
2.25.1
next prev parent reply other threads:[~2021-10-15 7:55 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 7:45 [PATCH v8 00/78] support vector extension v1.0 frank.chang
2021-10-15 7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-10-16 3:04 ` Richard Henderson
2021-10-17 22:55 ` Alistair Francis
2021-10-18 5:38 ` Richard Henderson
2021-10-18 6:01 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-15 7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-15 7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-15 7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-10-15 7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-15 7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-15 7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-15 7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-15 7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-15 7:45 ` frank.chang [this message]
2021-10-15 7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-15 7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-15 7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-15 7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-15 7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-18 5:44 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-15 7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang
2021-10-15 7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang
2021-10-15 7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-15 7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-18 5:46 ` Alistair Francis
2021-10-15 7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-18 5:47 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-18 5:53 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-18 5:49 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-18 5:54 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-21 4:28 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-21 4:24 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-21 4:26 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-21 4:27 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-25 6:08 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-25 6:13 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-15 7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-15 7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-15 7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-15 7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-25 6:16 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-26 6:29 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-26 6:30 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-26 6:32 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-25 6:43 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-15 7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-15 7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-10-15 7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-15 7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-15 7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-10-25 6:42 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-26 6:50 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-26 6:52 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-15 7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-15 7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-26 6:55 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-26 6:49 ` Alistair Francis
2021-10-15 9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang
2021-10-18 6:00 ` Alistair Francis
2021-10-18 6:09 ` Frank Chang
2021-10-18 6:12 ` Alistair Francis
2021-10-18 6:17 ` Frank Chang
2021-10-18 9:01 ` LIU Zhiwei
2021-10-18 9:34 ` LIU Zhiwei
2021-10-20 5:28 ` Alistair Francis
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