From: Alistair Francis <alistair23@gmail.com>
To: Frank Chang <frank.chang@sifive.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions
Date: Mon, 25 Oct 2021 16:16:48 +1000 [thread overview]
Message-ID: <CAKmqyKP1xkzuYkcNkENi3KUGS6-U71Ryfo0jNxVFN4paVYXb4w@mail.gmail.com> (raw)
In-Reply-To: <20211015074627.3957162-69-frank.chang@sifive.com>
On Fri, Oct 15, 2021 at 6:43 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Add the following instructions:
>
> * vfcvt.rtz.xu.f.v
> * vfcvt.rtz.x.f.v
>
> Also adjust GEN_OPFV_TRANS() to accept multiple floating-point rounding
> modes.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 11 ++--
> target/riscv/insn_trans/trans_rvv.c.inc | 84 +++++++++++++++----------
> 2 files changed, 59 insertions(+), 36 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 20b3095f56c..02064f8ec98 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -585,10 +585,13 @@ vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
> vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
> vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
> vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
> -vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
> -vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
> -vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
> -vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
> +
> +vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
> +vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
> +vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
> +vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
> +vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
> +vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
> vfwcvt_xu_f_v 100010 . ..... 01000 001 ..... 1010111 @r2_vm
> vfwcvt_x_f_v 100010 . ..... 01001 001 ..... 1010111 @r2_vm
> vfwcvt_f_xu_v 100010 . ..... 01010 001 ..... 1010111 @r2_vm
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 676336a5200..b1ea15517c0 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1,5 +1,4 @@
> /*
> - * RISC-V translation routines for the RVV Standard Extension.
> *
> * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
> *
> @@ -2368,34 +2367,41 @@ static bool opfv_check(DisasContext *s, arg_rmr *a)
> vext_check_ss(s, a->rd, a->rs2, a->vm);
> }
>
> -#define GEN_OPFV_TRANS(NAME, CHECK) \
> -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> -{ \
> - if (CHECK(s, a)) { \
> - uint32_t data = 0; \
> - static gen_helper_gvec_3_ptr * const fns[3] = { \
> - gen_helper_##NAME##_h, \
> - gen_helper_##NAME##_w, \
> - gen_helper_##NAME##_d, \
> - }; \
> - TCGLabel *over = gen_new_label(); \
> - gen_set_rm(s, RISCV_FRM_DYN); \
> - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
> - \
> - data = FIELD_DP32(data, VDATA, VM, a->vm); \
> - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
> - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
> - vreg_ofs(s, a->rs2), cpu_env, \
> - s->vlen / 8, s->vlen / 8, data, \
> - fns[s->sew - 1]); \
> - mark_vs_dirty(s); \
> - gen_set_label(over); \
> - return true; \
> - } \
> - return false; \
> +static bool do_opfv(DisasContext *s, arg_rmr *a,
> + gen_helper_gvec_3_ptr *fn,
> + bool (*checkfn)(DisasContext *, arg_rmr *),
> + int rm)
> +{
> + if (checkfn(s, a)) {
> + uint32_t data = 0;
> + TCGLabel *over = gen_new_label();
> + gen_set_rm(s, rm);
> + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
> +
> + data = FIELD_DP32(data, VDATA, VM, a->vm);
> + data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
> + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
> + vreg_ofs(s, a->rs2), cpu_env,
> + s->vlen / 8, s->vlen / 8, data, fn);
> + mark_vs_dirty(s);
> + gen_set_label(over);
> + return true;
> + }
> + return false;
> +}
> +
> +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \
> +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> +{ \
> + static gen_helper_gvec_3_ptr * const fns[3] = { \
> + gen_helper_##NAME##_h, \
> + gen_helper_##NAME##_w, \
> + gen_helper_##NAME##_d \
> + }; \
> + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \
> }
>
> -GEN_OPFV_TRANS(vfsqrt_v, opfv_check)
> +GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN)
>
> /* Vector Floating-Point MIN/MAX Instructions */
> GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
> @@ -2441,7 +2447,7 @@ GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
> GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
>
> /* Vector Floating-Point Classify Instruction */
> -GEN_OPFV_TRANS(vfclass_v, opfv_check)
> +GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN)
>
> /* Vector Floating-Point Merge Instruction */
> GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check)
> @@ -2495,10 +2501,24 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
> }
>
> /* Single-Width Floating-Point/Integer Type-Convert Instructions */
> -GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
> -GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
> -GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
> -GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
> +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \
> +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
> +{ \
> + static gen_helper_gvec_3_ptr * const fns[3] = { \
> + gen_helper_##HELPER##_h, \
> + gen_helper_##HELPER##_w, \
> + gen_helper_##HELPER##_d \
> + }; \
> + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \
> +}
> +
> +GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN)
> +GEN_OPFV_CVT_TRANS(vfcvt_x_f_v, vfcvt_x_f_v, RISCV_FRM_DYN)
> +GEN_OPFV_CVT_TRANS(vfcvt_f_xu_v, vfcvt_f_xu_v, RISCV_FRM_DYN)
> +GEN_OPFV_CVT_TRANS(vfcvt_f_x_v, vfcvt_f_x_v, RISCV_FRM_DYN)
> +/* Reuse the helper functions from vfcvt.xu.f.v and vfcvt.x.f.v */
> +GEN_OPFV_CVT_TRANS(vfcvt_rtz_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_RTZ)
> +GEN_OPFV_CVT_TRANS(vfcvt_rtz_x_f_v, vfcvt_x_f_v, RISCV_FRM_RTZ)
>
> /* Widening Floating-Point/Integer Type-Convert Instructions */
>
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-10-25 6:19 UTC|newest]
Thread overview: 120+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-15 7:45 [PATCH v8 00/78] support vector extension v1.0 frank.chang
2021-10-15 7:45 ` [PATCH v8 01/78] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh frank.chang
2021-10-16 3:04 ` Richard Henderson
2021-10-17 22:55 ` Alistair Francis
2021-10-18 5:38 ` Richard Henderson
2021-10-18 6:01 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 02/78] target/riscv: drop vector 0.7.1 and add 1.0 support frank.chang
2021-10-15 7:45 ` [PATCH v8 03/78] target/riscv: Use FIELD_EX32() to extract wd field frank.chang
2021-10-15 7:45 ` [PATCH v8 04/78] target/riscv: rvv-1.0: add mstatus VS field frank.chang
2021-10-15 7:45 ` [PATCH v8 05/78] target/riscv: rvv-1.0: add sstatus " frank.chang
2021-10-15 7:45 ` [PATCH v8 06/78] target/riscv: rvv-1.0: introduce writable misa.v field frank.chang
2021-10-15 7:45 ` [PATCH v8 07/78] target/riscv: rvv-1.0: add translation-time vector context status frank.chang
2021-10-15 7:45 ` [PATCH v8 08/78] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 09/78] target/riscv: rvv-1.0: add vcsr register frank.chang
2021-10-15 7:45 ` [PATCH v8 10/78] target/riscv: rvv-1.0: add vlenb register frank.chang
2021-10-15 7:45 ` [PATCH v8 11/78] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers frank.chang
2021-10-15 7:45 ` [PATCH v8 12/78] target/riscv: rvv-1.0: remove MLEN calculations frank.chang
2021-10-15 7:45 ` [PATCH v8 13/78] target/riscv: rvv-1.0: add fractional LMUL frank.chang
2021-10-15 7:45 ` [PATCH v8 14/78] target/riscv: rvv-1.0: add VMA and VTA frank.chang
2021-10-15 7:45 ` [PATCH v8 15/78] target/riscv: rvv-1.0: update check functions frank.chang
2021-10-15 7:45 ` [PATCH v8 16/78] target/riscv: introduce more imm value modes in translator functions frank.chang
2021-10-15 7:45 ` [PATCH v8 17/78] target/riscv: rvv:1.0: add translation-time nan-box helper function frank.chang
2021-10-15 7:45 ` [PATCH 18/76] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 18/78] target/riscv: rvv-1.0: remove amo operations instructions frank.chang
2021-10-18 5:44 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 19/78] target/riscv: rvv-1.0: configure instructions frank.chang
2021-10-15 7:45 ` [PATCH 19/76] target/riscv: rvv-1.0: stride load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 20/76] target/riscv: rvv-1.0: index " frank.chang
2021-10-15 7:45 ` [PATCH v8 20/78] target/riscv: rvv-1.0: stride " frank.chang
2021-10-15 7:45 ` [PATCH 21/76] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 21/78] target/riscv: rvv-1.0: index load and store instructions frank.chang
2021-10-15 7:45 ` [PATCH 22/76] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 22/78] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns frank.chang
2021-10-15 7:45 ` [PATCH 23/76] target/riscv: rvv-1.0: amo operations frank.chang
2021-10-15 7:45 ` [PATCH v8 23/78] target/riscv: rvv-1.0: fault-only-first unit stride load frank.chang
2021-10-15 7:45 ` [PATCH v8 24/78] target/riscv: rvv-1.0: load/store whole register instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 25/78] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns frank.chang
2021-10-15 7:45 ` [PATCH v8 26/78] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation frank.chang
2021-10-15 7:45 ` [PATCH v8 27/78] target/riscv: rvv-1.0: floating-point square-root instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 28/78] target/riscv: rvv-1.0: floating-point classify instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction frank.chang
2021-10-18 5:46 ` Alistair Francis
2021-10-15 7:45 ` [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction frank.chang
2021-10-18 5:47 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions frank.chang
2021-10-18 5:53 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction frank.chang
2021-10-18 5:49 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction frank.chang
2021-10-18 5:54 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended frank.chang
2021-10-21 4:28 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions frank.chang
2021-10-21 4:24 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction frank.chang
2021-10-15 7:45 ` [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions frank.chang
2021-10-21 4:26 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 39/78] target/riscv: rvv-1.0: whole register " frank.chang
2021-10-21 4:27 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow frank.chang
2021-10-25 6:08 ` Alistair Francis
2021-10-15 7:45 ` [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions frank.chang
2021-10-15 7:45 ` [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point " frank.chang
2021-10-25 6:13 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 53/78] target/riscv: rvv-1.0: single-width floating-point reduction frank.chang
2021-10-15 7:46 ` [PATCH v8 54/78] target/riscv: rvv-1.0: widening floating-point reduction instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 55/78] target/riscv: rvv-1.0: single-width scaling shift instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 56/78] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add frank.chang
2021-10-15 7:46 ` [PATCH v8 57/78] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf frank.chang
2021-10-15 7:46 ` [PATCH v8 58/78] target/riscv: rvv-1.0: remove integer extract instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 59/78] target/riscv: rvv-1.0: floating-point min/max instructions frank.chang
2021-10-15 7:46 ` [PATCH v8 60/78] target/riscv: introduce floating-point rounding mode enum frank.chang
2021-10-15 7:46 ` [PATCH v8 61/78] target/riscv: rvv-1.0: floating-point/integer type-convert instructions frank.chang
2021-10-25 6:16 ` Alistair Francis [this message]
2021-10-15 7:46 ` [PATCH v8 62/78] target/riscv: rvv-1.0: widening floating-point/integer type-convert frank.chang
2021-10-26 6:29 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 63/78] target/riscv: add "set round to odd" rounding mode helper function frank.chang
2021-10-26 6:30 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 64/78] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert frank.chang
2021-10-26 6:32 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits frank.chang
2021-10-25 6:43 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 66/78] target/riscv: rvv-1.0: implement vstart CSR frank.chang
2021-10-15 7:46 ` [PATCH v8 67/78] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid frank.chang
2021-10-15 7:46 ` [PATCH v8 68/78] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs frank.chang
2021-10-15 7:46 ` [PATCH v8 69/78] target/riscv: gdb: support vector registers for rv64 & rv32 frank.chang
2021-10-15 7:46 ` [PATCH v8 70/78] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction frank.chang
2021-10-15 7:46 ` [PATCH v8 71/78] target/riscv: rvv-1.0: floating-point reciprocal " frank.chang
2021-10-15 7:46 ` [PATCH v8 72/78] target/riscv: set mstatus.SD bit when writing fp CSRs frank.chang
2021-10-25 6:42 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 73/78] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 frank.chang
2021-10-26 6:50 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 74/78] target/riscv: rvv-1.0: add vsetivli instruction frank.chang
2021-10-26 6:52 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 75/78] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() frank.chang
2021-10-15 7:46 ` [PATCH v8 76/78] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns frank.chang
2021-10-15 7:46 ` [PATCH v8 77/78] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm frank.chang
2021-10-26 6:55 ` Alistair Francis
2021-10-15 7:46 ` [PATCH v8 78/78] target/riscv: rvv-1.0: update opivv_vadc_check() comment frank.chang
2021-10-26 6:49 ` Alistair Francis
2021-10-15 9:02 ` [PATCH v8 00/78] support vector extension v1.0 Frank Chang
2021-10-18 6:00 ` Alistair Francis
2021-10-18 6:09 ` Frank Chang
2021-10-18 6:12 ` Alistair Francis
2021-10-18 6:17 ` Frank Chang
2021-10-18 9:01 ` LIU Zhiwei
2021-10-18 9:34 ` LIU Zhiwei
2021-10-20 5:28 ` Alistair Francis
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