From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
Anup Patel <anup.patel@wdc.com>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v5 22/23] docs/system: riscv: Document AIA options for virt machine
Date: Sat, 11 Dec 2021 09:49:16 +0530 [thread overview]
Message-ID: <20211211041917.135345-23-anup.patel@wdc.com> (raw)
In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com>
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index fa016584bf..373645513a 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -63,6 +63,22 @@ The following machine-specific options are supported:
When this option is "on", ACLINT devices will be emulated instead of
SiFive CLINT. When not specified, this option is assumed to be "off".
+- aia=[none|aplic|aplic-imsic]
+
+ This option allows selecting interrupt controller defined by the AIA
+ (advanced interrupt architecture) specification. The "aia=aplic" selects
+ APLIC (advanced platform level interrupt controller) to handle wired
+ interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
+ message signaled interrupt controller) to handle both wired interrupts and
+ MSIs. When not specified, this option is assumed to be "none" which selects
+ SiFive PLIC to handle wired interrupts.
+
+- aia-guests=nnn
+
+ The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+ having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+ the default number of per-HART VS-level AIA IMSIC pages is 0.
+
Running Linux kernel
--------------------
--
2.25.1
next prev parent reply other threads:[~2021-12-11 4:33 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-11 4:18 [PATCH v5 00/23] QEMU RISC-V AIA support Anup Patel
2021-12-11 4:18 ` [PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-12-11 4:18 ` [PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-12-11 4:18 ` [PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-12-11 4:18 ` [PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-12-11 4:18 ` [PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 06/23] target/riscv: Add AIA cpu feature Anup Patel
2021-12-11 4:19 ` [PATCH v5 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2021-12-17 1:34 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-12-17 3:17 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-12-17 3:14 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-12-17 6:11 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-12-17 4:01 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-12-21 6:47 ` Alistair Francis
2021-12-22 9:21 ` Anup Patel
2021-12-11 4:19 ` [PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-12-15 1:08 ` Kip Walker
2021-12-15 14:59 ` Anup Patel
2021-12-11 4:19 ` [PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-12-11 4:19 ` [PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-12-11 4:19 ` [PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-12-11 4:19 ` Anup Patel [this message]
2021-12-11 4:19 ` [PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211211041917.135345-23-anup.patel@wdc.com \
--to=anup.patel@wdc.com \
--cc=Alistair.Francis@wdc.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=bmeng.cn@gmail.com \
--cc=palmer@dabbelt.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).