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From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Anup Patel <anup@brainfault.org>,
	Anup Patel <anup.patel@wdc.com>,
	qemu-devel@nongnu.org, Atish Patra <atishp@atishpatra.org>,
	Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Sat, 11 Dec 2021 09:49:17 +0530	[thread overview]
Message-ID: <20211211041917.135345-24-anup.patel@wdc.com> (raw)
In-Reply-To: <20211211041917.135345-1-anup.patel@wdc.com>

To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).

We also add a detailed source level comments about limit defines which
impact the physical address space utilization.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 hw/riscv/virt.c         | 10 ++++++++++
 include/hw/riscv/virt.h |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 74e9e333d1..68ab915525 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -44,6 +44,16 @@
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
 
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
 #define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
     IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e12e8ddcae..62d8e9c6d0 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
 #include "hw/block/flash.h"
 #include "qom/object.h"
 
-#define VIRT_CPUS_MAX_BITS             3
+#define VIRT_CPUS_MAX_BITS             9
 #define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
 #define VIRT_SOCKETS_MAX_BITS          2
 #define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
-- 
2.25.1



      parent reply	other threads:[~2021-12-11  4:35 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-11  4:18 [PATCH v5 00/23] QEMU RISC-V AIA support Anup Patel
2021-12-11  4:18 ` [PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-12-11  4:18 ` [PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-12-11  4:18 ` [PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-12-11  4:18 ` [PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-12-11  4:18 ` [PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-12-11  4:19 ` [PATCH v5 06/23] target/riscv: Add AIA cpu feature Anup Patel
2021-12-11  4:19 ` [PATCH v5 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2021-12-17  1:34   ` Alistair Francis
2021-12-11  4:19 ` [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-12-17  3:17   ` Alistair Francis
2021-12-11  4:19 ` [PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-12-17  3:14   ` Alistair Francis
2021-12-11  4:19 ` [PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-12-17  6:11   ` Alistair Francis
2021-12-11  4:19 ` [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-12-17  4:01   ` Alistair Francis
2021-12-11  4:19 ` [PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-12-11  4:19 ` [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-12-21  6:47   ` Alistair Francis
2021-12-22  9:21     ` Anup Patel
2021-12-11  4:19 ` [PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-12-11  4:19 ` [PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-12-11  4:19 ` [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-12-15  1:08   ` Kip Walker
2021-12-15 14:59     ` Anup Patel
2021-12-11  4:19 ` [PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-12-11  4:19 ` [PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-12-11  4:19 ` [PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-12-11  4:19 ` [PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-12-11  4:19 ` [PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-12-11  4:19 ` [PATCH v5 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2021-12-11  4:19 ` Anup Patel [this message]

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