From: Anup Patel <anup@brainfault.org>
To: Kip Walker <kip@rivosinc.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Anup Patel <anup.patel@wdc.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available
Date: Wed, 15 Dec 2021 20:29:38 +0530 [thread overview]
Message-ID: <CAAhSdy0KXNAFAxWgoozj73LP7_QO776PC5VEGzeuYzp+0Lk6RQ@mail.gmail.com> (raw)
In-Reply-To: <CABYrWZ95qCu8QiEfpQEy+=1cecLf+ruODAEg-vL8z58aBJffXw@mail.gmail.com>
On Wed, Dec 15, 2021 at 6:38 AM Kip Walker <kip@rivosinc.com> wrote:
>
> On Fri, Dec 10, 2021 at 8:35 PM Anup Patel <anup.patel@wdc.com> wrote:
> >
> > We should use the AIA INTC compatible string in the CPU INTC
> > DT nodes when the CPUs support AIA feature. This will allow
> > Linux INTC driver to use AIA local interrupt CSRs.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> > hw/riscv/virt.c | 13 +++++++++++--
> > 1 file changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 3af074148e..936156554c 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -211,8 +211,17 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
> > qemu_fdt_add_subnode(mc->fdt, intc_name);
> > qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle",
> > intc_phandles[cpu]);
> > - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
> > - "riscv,cpu-intc");
> > + if (riscv_feature(&s->soc[socket].harts[cpu].env,
> > + RISCV_FEATURE_AIA)) {
> > + static const char * const compat[2] = {
> > + "riscv,cpu-intc-aia", "riscv,cpu-intc"
> > + };
> > + qemu_fdt_setprop_string_array(mc->fdt, name, "compatible",
> > + (char **)&compat, ARRAY_SIZE(compat));
>
> I think this should be intc_name rather than name.
Ahh, good catch. I will fix this typo in the next revision.
Thanks,
Anup
>
> Kip
>
> > + } else {
> > + qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible",
> > + "riscv,cpu-intc");
> > + }
> > qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0);
> > qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1);
> >
> > --
> > 2.25.1
> >
> >
next prev parent reply other threads:[~2021-12-15 16:20 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-11 4:18 [PATCH v5 00/23] QEMU RISC-V AIA support Anup Patel
2021-12-11 4:18 ` [PATCH v5 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Anup Patel
2021-12-11 4:18 ` [PATCH v5 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs Anup Patel
2021-12-11 4:18 ` [PATCH v5 03/23] target/riscv: Implement hgeie and hgeip CSRs Anup Patel
2021-12-11 4:18 ` [PATCH v5 04/23] target/riscv: Improve delivery of guest external interrupts Anup Patel
2021-12-11 4:18 ` [PATCH v5 05/23] target/riscv: Allow setting CPU feature from machine/device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 06/23] target/riscv: Add AIA cpu feature Anup Patel
2021-12-11 4:19 ` [PATCH v5 07/23] target/riscv: Add defines for AIA CSRs Anup Patel
2021-12-17 1:34 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback Anup Patel
2021-12-17 3:17 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 09/23] target/riscv: Implement AIA local interrupt priorities Anup Patel
2021-12-17 3:14 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Anup Patel
2021-12-17 6:11 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs Anup Patel
2021-12-17 4:01 ` Alistair Francis
2021-12-11 4:19 ` [PATCH v5 12/23] target/riscv: Implement AIA interrupt filtering CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Anup Patel
2021-12-21 6:47 ` Alistair Francis
2021-12-22 9:21 ` Anup Patel
2021-12-11 4:19 ` [PATCH v5 14/23] target/riscv: Implement AIA xiselect and xireg CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 15/23] target/riscv: Implement AIA IMSIC interface CSRs Anup Patel
2021-12-11 4:19 ` [PATCH v5 16/23] hw/riscv: virt: Use AIA INTC compatible string when available Anup Patel
2021-12-15 1:08 ` Kip Walker
2021-12-15 14:59 ` Anup Patel [this message]
2021-12-11 4:19 ` [PATCH v5 17/23] target/riscv: Allow users to force enable AIA CSRs in HART Anup Patel
2021-12-11 4:19 ` [PATCH v5 18/23] hw/intc: Add RISC-V AIA APLIC device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2021-12-11 4:19 ` [PATCH v5 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2021-12-11 4:19 ` [PATCH v5 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2021-12-11 4:19 ` [PATCH v5 22/23] docs/system: riscv: Document AIA options for " Anup Patel
2021-12-11 4:19 ` [PATCH v5 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs Anup Patel
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