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From: Peter Delevoryas <me@pjd.dev>
Cc: clg@kaod.org, peter.maydell@linaro.org, andrew@aj.id.au,
	joel@jms.id.au, cminyard@mvista.com, titusr@google.com,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org, zhdaniel@fb.com,
	pdel@fb.com
Subject: [PATCH v3 02/14] hw/i2c/aspeed: Fix DMA len write-enable bit handling
Date: Wed, 29 Jun 2022 21:51:21 -0700	[thread overview]
Message-ID: <20220630045133.32251-3-me@pjd.dev> (raw)
In-Reply-To: <20220630045133.32251-1-me@pjd.dev>

From: Peter Delevoryas <pdel@fb.com>

I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]

/* 0x1C : I2CM Master DMA Transfer Length Register   */

I think we should be checking the write-enable bits on the incoming
value, not checking the register array. I'm not sure we're even writing
the write-enable bits to the register array, actually.

[1] https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148

Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
---
 hw/i2c/aspeed_i2c.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
index ff33571954..cbaa7c96fc 100644
--- a/hw/i2c/aspeed_i2c.c
+++ b/hw/i2c/aspeed_i2c.c
@@ -644,18 +644,18 @@ static void aspeed_i2c_bus_new_write(AspeedI2CBus *bus, hwaddr offset,
                                                      RX_BUF_LEN) + 1;
         break;
     case A_I2CM_DMA_LEN:
-        w1t = ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
-                   ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
+        w1t = FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T) ||
+              FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T);
         /* If none of the w1t bits are set, just write to the reg as normal. */
         if (!w1t) {
             bus->regs[R_I2CM_DMA_LEN] = value;
             break;
         }
-        if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
+        if (FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN_W1T)) {
             ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, RX_BUF_LEN,
                              FIELD_EX32(value, I2CM_DMA_LEN, RX_BUF_LEN));
         }
-        if (ARRAY_FIELD_EX32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
+        if (FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN_W1T)) {
             ARRAY_FIELD_DP32(bus->regs, I2CM_DMA_LEN, TX_BUF_LEN,
                              FIELD_EX32(value, I2CM_DMA_LEN, TX_BUF_LEN));
         }
-- 
2.37.0



  parent reply	other threads:[~2022-06-30  4:57 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-30  4:51 [PATCH v3 00/14] hw/i2c/aspeed: I2C slave mode DMA RX w/ new regs Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 01/14] hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference Peter Delevoryas
2022-06-30  4:51 ` Peter Delevoryas [this message]
2022-06-30  4:51 ` [PATCH v3 03/14] hw/i2c/aspeed: Fix MASTER_EN missing error message Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 04/14] hw/i2c: support multiple masters Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 05/14] hw/i2c: add asynchronous send Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 06/14] hw/i2c/aspeed: add slave device in old register mode Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 07/14] hw/i2c/aspeed: Add new-registers DMA slave mode RX support Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 08/14] hw/i2c/pmbus: Add idle state to return 0xff's Peter Delevoryas
2022-06-30 19:18   ` Titus Rwantare
2022-06-30  4:51 ` [PATCH v3 09/14] hw/sensor: Add IC_DEVICE_ID to ISL voltage regulators Peter Delevoryas
2022-06-30 19:20   ` Titus Rwantare
2022-06-30  4:51 ` [PATCH v3 10/14] hw/sensor: Add Renesas ISL69259 device model Peter Delevoryas
2022-06-30  6:30   ` Cédric Le Goater
2022-06-30 19:16     ` Titus Rwantare
2022-07-01  5:35       ` Cédric Le Goater
2022-06-30 19:16   ` Titus Rwantare
2022-06-30 21:14     ` Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 11/14] hw/misc/aspeed: Add PECI controller Peter Delevoryas
2022-06-30  6:32   ` Cédric Le Goater
2022-06-30  4:51 ` [PATCH v3 12/14] hw/misc/aspeed: Add fby35-sb-cpld Peter Delevoryas
2022-06-30  6:47   ` Cédric Le Goater
2022-06-30  4:51 ` [PATCH v3 13/14] hw/misc/aspeed: Add intel-me Peter Delevoryas
2022-06-30 11:09   ` Cédric Le Goater
2022-06-30 16:20     ` Peter Delevoryas
2022-06-30  4:51 ` [PATCH v3 14/14] hw/arm/aspeed: Add oby35-cl machine Peter Delevoryas
2022-06-30 11:02   ` Cédric Le Goater
2022-06-30 16:15     ` Peter Delevoryas
2022-06-30 16:42       ` Cédric Le Goater
2022-06-30 17:48         ` Peter Delevoryas
2022-06-30 23:06         ` Peter Delevoryas
2022-07-01  5:39           ` Cédric Le Goater
2022-06-30  6:13 ` [PATCH v3 00/14] hw/i2c/aspeed: I2C slave mode DMA RX w/ new regs Cédric Le Goater
2022-06-30  7:50 ` Cédric Le Goater

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