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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH v2 02/11] target/arm: enable tracking of CPU index in MemTxAttrs
Date: Mon, 26 Sep 2022 14:38:55 +0100	[thread overview]
Message-ID: <20220926133904.3297263-3-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org>

Both arm_cpu_tlb_fill (for normal IO) and
arm_cpu_get_phys_page_attrs_debug (for debug access) come through
get_phys_addr which is setting the other memory attributes for the
transaction. As these are all by definition CPU accesses we can also
set the requested_type/index as appropriate.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/arm/ptw.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3261039d93..644d450662 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -2315,6 +2315,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
 {
     ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
 
+    attrs->requester_type = MEMTXATTRS_CPU;
+    attrs->requester_id = env_cpu(env)->cpu_index;
+
     if (mmu_idx != s1_mmu_idx) {
         /*
          * Call ourselves recursively to do the stage 1 and then stage 2
-- 
2.34.1



  parent reply	other threads:[~2022-09-26 14:25 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 13:38 [PATCH v2 00/11] gdbstub/next (MemTxAttrs and re-factoring) Alex Bennée
2022-09-26 13:38 ` [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-09-26 14:34   ` Peter Maydell
2022-09-26 15:09     ` Alex Bennée
2022-09-26 15:30       ` Peter Maydell
2022-09-26 20:15   ` Alexander Graf
2022-09-26 13:38 ` Alex Bennée [this message]
2022-09-26 14:12   ` [PATCH v2 02/11] target/arm: enable tracking of " Peter Maydell
2022-09-26 15:05     ` Alex Bennée
2022-09-26 15:07       ` Peter Maydell
2022-09-26 13:38 ` [PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs Alex Bennée
2022-09-26 14:10   ` Peter Maydell
2022-09-26 15:46     ` Alex Bennée
2022-09-26 20:19   ` Alexander Graf
2022-09-26 13:38 ` [PATCH v2 04/11] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-09-27  9:45   ` Thomas Huth
2022-09-26 13:38 ` [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-09-26 14:14   ` Peter Maydell
2022-09-26 15:06     ` Alex Bennée
2022-09-26 15:18       ` Peter Maydell
2022-09-26 15:41         ` Alex Bennée
2022-09-26 15:45           ` Peter Maydell
2022-09-26 13:38 ` [PATCH v2 06/11] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-09-26 13:39 ` [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak Alex Bennée
2022-09-26 13:39 ` [PATCH v2 08/11] gdbstub: move into its own sub directory Alex Bennée
2022-09-26 13:39 ` [PATCH v2 09/11] gdbstub: move sstep flags probing into AccelClass Alex Bennée
2022-09-26 13:39 ` [PATCH v2 10/11] gdbstub: move breakpoint logic to accel ops Alex Bennée
2022-09-26 13:39 ` [PATCH v2 11/11] gdbstub: move guest debug support check to ops Alex Bennée

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