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From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: f4bug@amsat.org, mads@ynddal.dk, qemu-arm@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Alexander Graf" <agraf@csgraf.de>,
	"Peter Maydell" <peter.maydell@linaro.org>
Subject: [PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs
Date: Mon, 26 Sep 2022 14:38:56 +0100	[thread overview]
Message-ID: <20220926133904.3297263-4-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220926133904.3297263-1-alex.bennee@linaro.org>

As most HVF devices are done purely in software we need to make sure
we properly encode the source CPU in MemTxAttrs. This will allow the
device emulations to use those attributes rather than relying on
current_cpu (although current_cpu will still be correct in this case).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Mads Ynddal <mads@ynddal.dk>
Cc: Alexander Graf <agraf@csgraf.de>
---
 target/arm/hvf/hvf.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 060aa0ccf4..13b7971560 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -1233,11 +1233,11 @@ int hvf_vcpu_exec(CPUState *cpu)
             val = hvf_get_reg(cpu, srt);
             address_space_write(&address_space_memory,
                                 hvf_exit->exception.physical_address,
-                                MEMTXATTRS_UNSPECIFIED, &val, len);
+                                MEMTXATTRS_CPU(cpu->cpu_index), &val, len);
         } else {
             address_space_read(&address_space_memory,
                                hvf_exit->exception.physical_address,
-                               MEMTXATTRS_UNSPECIFIED, &val, len);
+                               MEMTXATTRS_CPU(cpu->cpu_index), &val, len);
             hvf_set_reg(cpu, srt, val);
         }
 
-- 
2.34.1



  parent reply	other threads:[~2022-09-26 14:21 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-26 13:38 [PATCH v2 00/11] gdbstub/next (MemTxAttrs and re-factoring) Alex Bennée
2022-09-26 13:38 ` [PATCH v2 01/11] hw: encode accessing CPU index in MemTxAttrs Alex Bennée
2022-09-26 14:34   ` Peter Maydell
2022-09-26 15:09     ` Alex Bennée
2022-09-26 15:30       ` Peter Maydell
2022-09-26 20:15   ` Alexander Graf
2022-09-26 13:38 ` [PATCH v2 02/11] target/arm: enable tracking of " Alex Bennée
2022-09-26 14:12   ` Peter Maydell
2022-09-26 15:05     ` Alex Bennée
2022-09-26 15:07       ` Peter Maydell
2022-09-26 13:38 ` Alex Bennée [this message]
2022-09-26 14:10   ` [PATCH v2 03/11] target/arm: ensure HVF traps set appropriate MemTxAttrs Peter Maydell
2022-09-26 15:46     ` Alex Bennée
2022-09-26 20:19   ` Alexander Graf
2022-09-26 13:38 ` [PATCH v2 04/11] qtest: make read/write operation appear to be from CPU Alex Bennée
2022-09-27  9:45   ` Thomas Huth
2022-09-26 13:38 ` [PATCH v2 05/11] hw/intc/gic: use MxTxAttrs to divine accessing CPU Alex Bennée
2022-09-26 14:14   ` Peter Maydell
2022-09-26 15:06     ` Alex Bennée
2022-09-26 15:18       ` Peter Maydell
2022-09-26 15:41         ` Alex Bennée
2022-09-26 15:45           ` Peter Maydell
2022-09-26 13:38 ` [PATCH v2 06/11] hw/timer: convert mptimer access to attrs to derive cpu index Alex Bennée
2022-09-26 13:39 ` [PATCH v2 07/11] configure: move detected gdb to TCG's config-host.mak Alex Bennée
2022-09-26 13:39 ` [PATCH v2 08/11] gdbstub: move into its own sub directory Alex Bennée
2022-09-26 13:39 ` [PATCH v2 09/11] gdbstub: move sstep flags probing into AccelClass Alex Bennée
2022-09-26 13:39 ` [PATCH v2 10/11] gdbstub: move breakpoint logic to accel ops Alex Bennée
2022-09-26 13:39 ` [PATCH v2 11/11] gdbstub: move guest debug support check to ops Alex Bennée

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