From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()
Date: Mon, 27 Mar 2023 09:42:45 -0300 [thread overview]
Message-ID: <20230327124247.106595-18-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com>
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 81c8e0d541..3078d1a097 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -397,11 +397,10 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, MXL_RV64, RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.ext_g = true;
- cpu->cfg.ext_icsr = true;
cpu->cfg.ext_zfh = true;
cpu->cfg.mmu = true;
cpu->cfg.ext_xtheadba = true;
--
2.39.2
next prev parent reply other threads:[~2023-03-27 12:45 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 12:42 [PATCH 00/19] remove MISA ext_N flags from cpu->cfg Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 02/19] target/riscv: remove MISA properties from isa_edata_arr[] Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-03-27 18:43 ` Richard Henderson
2023-03-27 18:59 ` Daniel Henrique Barboza
2023-03-27 18:52 ` Richard Henderson
2023-03-27 22:15 ` Daniel Henrique Barboza
2023-03-27 22:27 ` Richard Henderson
2023-03-27 12:42 ` [PATCH 04/19] target/riscv: remove cpu->cfg.ext_a Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 05/19] target/riscv: remove cpu->cfg.ext_c Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 06/19] target/riscv: remove cpu->cfg.ext_d Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 07/19] target/riscv: remove cpu->cfg.ext_f Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 08/19] target/riscv: remove cpu->cfg.ext_i Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 09/19] target/riscv: remove cpu->cfg.ext_e Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 10/19] target/riscv: remove cpu->cfg.ext_m Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 11/19] target/riscv: remove cpu->cfg.ext_s Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 12/19] target/riscv: remove cpu->cfg.ext_u Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 13/19] target/riscv: remove cpu->cfg.ext_h Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 14/19] target/riscv: remove cpu->cfg.ext_j Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 15/19] target/riscv: remove cpu->cfg.ext_v Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg() Daniel Henrique Barboza
2023-03-27 12:42 ` Daniel Henrique Barboza [this message]
2023-03-27 12:42 ` [PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
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