From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
bmeng@tinylab.org, liweiwei@iscas.ac.cn,
zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Subject: [PATCH 04/19] target/riscv: remove cpu->cfg.ext_a
Date: Mon, 27 Mar 2023 09:42:32 -0300 [thread overview]
Message-ID: <20230327124247.106595-5-dbarboza@ventanamicro.com> (raw)
In-Reply-To: <20230327124247.106595-1-dbarboza@ventanamicro.com>
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 16 ++++++++--------
target/riscv/cpu.h | 1 -
2 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c33ba86085..d2484396c4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -813,13 +813,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* Do some ISA extension error checking */
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m &&
- cpu->cfg.ext_a && cpu->cfg.ext_f &&
- cpu->cfg.ext_d &&
+ riscv_has_ext(env, RVA) &&
+ cpu->cfg.ext_f && cpu->cfg.ext_d &&
cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
cpu->cfg.ext_i = true;
cpu->cfg.ext_m = true;
- cpu->cfg.ext_a = true;
cpu->cfg.ext_f = true;
cpu->cfg.ext_d = true;
cpu->cfg.ext_icsr = true;
@@ -863,7 +862,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
return;
}
- if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) {
+ if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
error_setg(errp, "Zawrs extension requires A extension");
return;
}
@@ -1101,7 +1100,7 @@ static void riscv_cpu_sync_misa_cfg(CPURISCVState *env)
if (riscv_cpu_cfg(env)->ext_m) {
ext |= RVM;
}
- if (riscv_cpu_cfg(env)->ext_a) {
+ if (riscv_has_ext(env, RVA)) {
ext |= RVA;
}
if (riscv_cpu_cfg(env)->ext_f) {
@@ -1437,7 +1436,10 @@ static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
visit_type_bool(v, name, &value, errp);
}
-static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {};
+static RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
+ {.name = "a", .description = "Atomic instructions",
+ .misa_bit = RVA, .enabled = true},
+};
static void riscv_cpu_add_misa_properties(Object *cpu_obj)
{
@@ -1463,7 +1465,6 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false),
DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
- DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
@@ -1577,7 +1578,6 @@ static void register_cpu_props(Object *obj)
cpu->cfg.ext_i = misa_ext & RVI;
cpu->cfg.ext_e = misa_ext & RVE;
cpu->cfg.ext_m = misa_ext & RVM;
- cpu->cfg.ext_a = misa_ext & RVA;
cpu->cfg.ext_f = misa_ext & RVF;
cpu->cfg.ext_d = misa_ext & RVD;
cpu->cfg.ext_v = misa_ext & RVV;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..f703888310 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -422,7 +422,6 @@ struct RISCVCPUConfig {
bool ext_e;
bool ext_g;
bool ext_m;
- bool ext_a;
bool ext_f;
bool ext_d;
bool ext_c;
--
2.39.2
next prev parent reply other threads:[~2023-03-27 12:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-27 12:42 [PATCH 00/19] remove MISA ext_N flags from cpu->cfg Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 01/19] target/riscv: sync env->misa_ext* with cpu->cfg in realize() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 02/19] target/riscv: remove MISA properties from isa_edata_arr[] Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 03/19] target/riscv: introduce riscv_cpu_add_misa_properties() Daniel Henrique Barboza
2023-03-27 18:43 ` Richard Henderson
2023-03-27 18:59 ` Daniel Henrique Barboza
2023-03-27 18:52 ` Richard Henderson
2023-03-27 22:15 ` Daniel Henrique Barboza
2023-03-27 22:27 ` Richard Henderson
2023-03-27 12:42 ` Daniel Henrique Barboza [this message]
2023-03-27 12:42 ` [PATCH 05/19] target/riscv: remove cpu->cfg.ext_c Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 06/19] target/riscv: remove cpu->cfg.ext_d Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 07/19] target/riscv: remove cpu->cfg.ext_f Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 08/19] target/riscv: remove cpu->cfg.ext_i Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 09/19] target/riscv: remove cpu->cfg.ext_e Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 10/19] target/riscv: remove cpu->cfg.ext_m Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 11/19] target/riscv: remove cpu->cfg.ext_s Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 12/19] target/riscv: remove cpu->cfg.ext_u Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 13/19] target/riscv: remove cpu->cfg.ext_h Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 14/19] target/riscv: remove cpu->cfg.ext_j Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 15/19] target/riscv: remove cpu->cfg.ext_v Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 16/19] target/riscv: remove riscv_cpu_sync_misa_cfg() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 17/19] target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 18/19] target/riscv: add RVG and remove cpu->cfg.ext_g Daniel Henrique Barboza
2023-03-27 12:42 ` [PATCH 19/19] target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza
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