Re: [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU

[LIU Zhiwei <zhiwei_liu@c-sky.com>]

On 2020/5/20 5:31, Alistair Francis wrote:
> Ibex is a small and efficient, 32-bit, in-order RISC-V core with
> a 2-stage pipeline that implements the RV32IMC instruction set
> architecture.
>
> For more details on lowRISC see here:
> https://github.com/lowRISC/ibex
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
>   target/riscv/cpu.h |  1 +
>   target/riscv/cpu.c | 10 ++++++++++
>   2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0e7f5b9c5..8733d7467f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -35,6 +35,7 @@
>   #define TYPE_RISCV_CPU_ANY              RISCV_CPU_TYPE_NAME("any")
>   #define TYPE_RISCV_CPU_BASE32           RISCV_CPU_TYPE_NAME("rv32")
>   #define TYPE_RISCV_CPU_BASE64           RISCV_CPU_TYPE_NAME("rv64")
> +#define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
>   #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
>   #define TYPE_RISCV_CPU_SIFIVE_E34       RISCV_CPU_TYPE_NAME("sifive-e34")
>   #define TYPE_RISCV_CPU_SIFIVE_E51       RISCV_CPU_TYPE_NAME("sifive-e51")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 5eb3c02735..eb2bbc87ae 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -156,6 +156,15 @@ static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
>       set_feature(env, RISCV_FEATURE_PMP);
>   }
>   
> +static void rv32imcu_nommu_cpu_init(Object *obj)
> +{
> +    CPURISCVState *env = &RISCV_CPU(obj)->env;
> +    set_misa(env, RV32 | RVI | RVM | RVC | RVU);
> +    set_priv_version(env, PRIV_VERSION_1_10_0);
> +    set_resetvec(env, 0x8090);
Hi Alistair,

I see all RISC-V cpus  have an reset vector which acts as the first pc 
when machine boots up.
However, the first pc is more like an attribute of a machine, not a cpu.

Another reason is that the cpu names are a combination of ISA.
Then the cpus from different vendors may have same ISA, with different 
reset vectors.

Do you think so?

Zhiwei
> +    set_feature(env, RISCV_FEATURE_PMP);
> +}
> +
>   static void rv32imacu_nommu_cpu_init(Object *obj)
>   {
>       CPURISCVState *env = &RISCV_CPU(obj)->env;
> @@ -619,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>       DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
>   #if defined(TARGET_RISCV32)
>       DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base32_cpu_init),
> +    DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32imcu_nommu_cpu_init),
>       DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
>       DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),
>       DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),