From: Alistair Francis <alistair23@gmail.com>
To: "Philippe Mathieu-Daudé" <philmd@redhat.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: Re: [PATCH v3 1/9] riscv/boot: Add a missing header include
Date: Wed, 20 May 2020 09:09:29 -0700 [thread overview]
Message-ID: <CAKmqyKPLL9=xm2sfdgZcovx3m_F8NEE+NC3vZyigbOk7QQyQKQ@mail.gmail.com> (raw)
In-Reply-To: <0fcaef83-ec31-d5f5-4677-d42a77d90e3e@redhat.com>
On Tue, May 19, 2020 at 11:01 PM Philippe Mathieu-Daudé
<philmd@redhat.com> wrote:
>
> On 5/19/20 11:31 PM, Alistair Francis wrote:
> > Currently every c file that includes boot.h also includes loader.h
> > before it. Which is why the build works fine. We should be able to
> > include just boot.h though so this is a small fixup to allow that.
>
> What about:
>
> 'As the functions declared in this header use the symbol_fn_t
> typedef itself declared in "hw/loader.h", we need to include
> it here to make the header file self-contained.'
Sounds good.
Alistair
>
> >
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> > ---
> > include/hw/riscv/boot.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
> > index 474a940ad5..9daa98da08 100644
> > --- a/include/hw/riscv/boot.h
> > +++ b/include/hw/riscv/boot.h
> > @@ -21,6 +21,7 @@
> > #define RISCV_BOOT_H
> >
> > #include "exec/cpu-defs.h"
> > +#include "hw/loader.h"
> >
> > void riscv_find_and_load_firmware(MachineState *machine,
> > const char *default_machine_firmware,
> >
>
next prev parent reply other threads:[~2020-05-20 16:19 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 21:31 [PATCH v3 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 1/9] riscv/boot: Add a missing header include Alistair Francis
2020-05-20 6:01 ` Philippe Mathieu-Daudé
2020-05-20 16:09 ` Alistair Francis [this message]
2020-05-19 21:31 ` [PATCH v3 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-21 1:45 ` Bin Meng
2020-05-19 21:31 ` [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-22 7:50 ` LIU Zhiwei
2020-05-26 17:12 ` Alistair Francis
2020-05-27 1:58 ` LIU Zhiwei
2020-05-27 16:44 ` Alistair Francis
2020-05-19 21:31 ` [PATCH v3 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 5/9] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-19 21:31 ` [PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-19 21:31 ` [PATCH v3 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé
2020-05-19 21:31 ` [PATCH v3 8/9] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé
2020-05-19 21:31 ` [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-21 1:52 ` Bin Meng
2020-05-27 0:51 ` Alistair Francis
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