From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v3 8/9] riscv/opentitan: Connect the UART device
Date: Wed, 20 May 2020 08:03:59 +0200 [thread overview]
Message-ID: <47d26423-bf54-c0af-5043-5e6a93ead552@amsat.org> (raw)
In-Reply-To: <eb6069a05d18f4a1c9c7dbc97a0c521ae4b3674f.1589923785.git.alistair.francis@wdc.com>
On 5/19/20 11:31 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
> include/hw/riscv/opentitan.h | 13 +++++++++++++
> hw/riscv/opentitan.c | 24 ++++++++++++++++++++++--
> 2 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 8d6a09b696..825a3610bc 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -21,6 +21,7 @@
>
> #include "hw/riscv/riscv_hart.h"
> #include "hw/intc/ibex_plic.h"
> +#include "hw/char/ibex_uart.h"
>
> #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
> #define RISCV_IBEX_SOC(obj) \
> @@ -33,6 +34,7 @@ typedef struct LowRISCIbexSoCState {
> /*< public >*/
> RISCVHartArrayState cpus;
> IbexPlicState plic;
> + IbexUartState uart;
>
> MemoryRegion flash_mem;
> MemoryRegion rom;
> @@ -63,4 +65,15 @@ enum {
> IBEX_USBDEV,
> };
>
> +enum {
> + IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,
> + IBEX_UART_RX_TIMEOUT_IRQ = 0x27,
> + IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,
> + IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,
> + IBEX_UART_RX_OVERFLOW_IRQ = 0x24,
> + IBEX_UART_TX_EMPTY_IRQ = 0x23,
> + IBEX_UART_RX_WATERMARK_IRQ = 0x22,
> + IBEX_UART_TX_WATERMARK_IRQ = 0x21
> +};
> +
> #endif
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 3926321d8c..a6c0b949ca 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -96,6 +96,9 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj)
>
> sysbus_init_child_obj(obj, "plic", &s->plic,
> sizeof(s->plic), TYPE_IBEX_PLIC);
> +
> + sysbus_init_child_obj(obj, "uart", &s->uart,
> + sizeof(s->uart), TYPE_IBEX_UART);
> }
>
> static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> @@ -137,8 +140,25 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> busdev = SYS_BUS_DEVICE(dev);
> sysbus_mmio_map(busdev, 0, memmap[IBEX_PLIC].base);
>
> - create_unimplemented_device("riscv.lowrisc.ibex.uart",
> - memmap[IBEX_UART].base, memmap[IBEX_UART].size);
> + /* UART */
> + dev = DEVICE(&(s->uart));
> + qdev_prop_set_chr(dev, "chardev", serial_hd(0));
> + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err);
> + if (err != NULL) {
> + error_propagate(errp, err);
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, memmap[IBEX_UART].base);
> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_UART_TX_WATERMARK_IRQ));
> + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_UART_RX_WATERMARK_IRQ));
> + sysbus_connect_irq(busdev, 2, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_UART_TX_EMPTY_IRQ));
> + sysbus_connect_irq(busdev, 3, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_UART_RX_OVERFLOW_IRQ));
> +
> create_unimplemented_device("riscv.lowrisc.ibex.gpio",
> memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
> create_unimplemented_device("riscv.lowrisc.ibex.spi",
>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
next prev parent reply other threads:[~2020-05-20 6:05 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 21:31 [PATCH v3 0/9] RISC-V Add the OpenTitan Machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 1/9] riscv/boot: Add a missing header include Alistair Francis
2020-05-20 6:01 ` Philippe Mathieu-Daudé
2020-05-20 16:09 ` Alistair Francis
2020-05-19 21:31 ` [PATCH v3 2/9] target/riscv: Don't overwrite the reset vector Alistair Francis
2020-05-21 1:45 ` Bin Meng
2020-05-19 21:31 ` [PATCH v3 3/9] target/riscv: Add the lowRISC Ibex CPU Alistair Francis
2020-05-22 7:50 ` LIU Zhiwei
2020-05-26 17:12 ` Alistair Francis
2020-05-27 1:58 ` LIU Zhiwei
2020-05-27 16:44 ` Alistair Francis
2020-05-19 21:31 ` [PATCH v3 4/9] riscv: Initial commit of OpenTitan machine Alistair Francis
2020-05-19 21:31 ` [PATCH v3 5/9] hw/char: Initial commit of Ibex UART Alistair Francis
2020-05-19 21:31 ` [PATCH v3 6/9] hw/intc: Initial commit of lowRISC Ibex PLIC Alistair Francis
2020-05-19 21:31 ` [PATCH v3 7/9] riscv/opentitan: Connect the PLIC device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé
2020-05-19 21:31 ` [PATCH v3 8/9] riscv/opentitan: Connect the UART device Alistair Francis
2020-05-20 6:03 ` Philippe Mathieu-Daudé [this message]
2020-05-19 21:31 ` [PATCH v3 9/9] target/riscv: Use a smaller guess size for no-MMU PMP Alistair Francis
2020-05-21 1:52 ` Bin Meng
2020-05-27 0:51 ` Alistair Francis
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