From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Luc Michel <luc@lmichel.fr>
Cc: Peter Maydell <peter.maydell@linaro.org>,
qemu-devel@nongnu.org,
Andrew Baumann <Andrew.Baumann@microsoft.com>,
Paul Zimmerman <pauldzim@gmail.com>,
Niek Linnenbank <nieklinnenbank@gmail.com>,
qemu-arm@nongnu.org, Havard Skinnemoen <hskinnemoen@google.com>
Subject: Re: [PATCH v3 13/15] hw/misc/bcm2835_cprman: add sane reset values to the registers
Date: Fri, 16 Oct 2020 19:10:37 +0200 [thread overview]
Message-ID: <473818a2-b267-881f-b827-425a384a27bd@amsat.org> (raw)
In-Reply-To: <20201011182608.gfmfvdioiyyaxrfq@sekoia-pc.home.lmichel.fr>
On 10/11/20 8:26 PM, Luc Michel wrote:
> On 18:18 Sat 10 Oct , Philippe Mathieu-Daudé wrote:
>> On 10/10/20 3:57 PM, Luc Michel wrote:
>>> Those reset values have been extracted from a Raspberry Pi 3 model B
>>> v1.2, using the 2020-08-20 version of raspios. The dump was done using
>>> the debugfs interface of the CPRMAN driver in Linux (under
>>> '/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels
>>> and muxes) can be observed by reading the 'regdump' file (e.g.
>>> 'plla/regdump').
>>>
>>> Those values are set by the Raspberry Pi firmware at boot time (Linux
>>> expects them to be set when it boots up).
>>>
>>> Some stages are not exposed by the Linux driver (e.g. the PLL B). For
>>> those, the reset values are unknown and left to 0 which implies a
>>> disabled output.
>>>
>>> Once booted in QEMU, the final clock tree is very similar to the one
>>> visible on real hardware. The differences come from some unimplemented
>>> devices for which the driver simply disable the corresponding clock.
>>>
>>> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>> Signed-off-by: Luc Michel <luc@lmichel.fr>
>>> ---
>>> include/hw/misc/bcm2835_cprman_internals.h | 269 +++++++++++++++++++++
>>> hw/misc/bcm2835_cprman.c | 31 +++
>>> 2 files changed, 300 insertions(+)
>>>
>>> diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/bcm2835_cprman_internals.h
>>> index a6e799075f..339759b307 100644
>>> --- a/include/hw/misc/bcm2835_cprman_internals.h
>>> +++ b/include/hw/misc/bcm2835_cprman_internals.h
>>> @@ -745,6 +745,275 @@ static inline void set_clock_mux_init_info(BCM2835CprmanState *s,
>>> mux->reg_div = &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset + 1];
>>> mux->int_bits = CLOCK_MUX_INIT_INFO[id].int_bits;
>>> mux->frac_bits = CLOCK_MUX_INIT_INFO[id].frac_bits;
>>> }
>>> +
>>> +/*
>>> + * Object reset info
>>> + * Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using the
>>> + * clk debugfs interface in Linux.
>>> + */
>>> +typedef struct PLLResetInfo {
>>> + uint32_t cm;
>>> + uint32_t a2w_ctrl;
>>> + uint32_t a2w_ana[4];
>>> + uint32_t a2w_frac;
>>> +} PLLResetInfo;
>>> +
>>> +static const PLLResetInfo PLL_RESET_INFO[] = {
>>> + [CPRMAN_PLLA] = {
>>> + .cm = 0x0000008a,
>>> + .a2w_ctrl = 0x0002103a,
>>> + .a2w_frac = 0x00098000,
>>> + .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
>>> + },
>>> +
>>> + [CPRMAN_PLLC] = {
>>> + .cm = 0x00000228,
>>> + .a2w_ctrl = 0x0002103e,
>>> + .a2w_frac = 0x00080000,
>>> + .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
>>> + },
>>> +
>>> + [CPRMAN_PLLD] = {
>>> + .cm = 0x0000020a,
>>> + .a2w_ctrl = 0x00021034,
>>> + .a2w_frac = 0x00015556,
>>> + .a2w_ana = { 0x00000000, 0x00144000, 0x00000000, 0x00000100 }
>>> + },
>>> +
>>> + [CPRMAN_PLLH] = {
>>> + .cm = 0x00000000,
>>> + .a2w_ctrl = 0x0002102d,
>>> + .a2w_frac = 0x00000000,
>>> + .a2w_ana = { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 }
>>> + },
>>> +
>>> + [CPRMAN_PLLB] = {
>>> + /* unknown */
>>> + .cm = 0x00000000,
>>> + .a2w_ctrl = 0x00000000,
>>> + .a2w_frac = 0x00000000,
>>> + .a2w_ana = { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }
>>> + }
>>> +};
>>> +
>>> +typedef struct PLLChannelResetInfo {
>>> + /*
>>> + * Even though a PLL channel has a CM register, it shares it with its
>>> + * parent PLL. The parent already takes care of the reset value.
>>> + */
>>> + uint32_t a2w_ctrl;
>>> +} PLLChannelResetInfo;
>>> +
>>> +static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] = {
>>> + [CPRMAN_PLLA_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
>>> + [CPRMAN_PLLA_CHANNEL_CORE] = { .a2w_ctrl = 0x00000003 },
>>> + [CPRMAN_PLLA_CHANNEL_PER] = { .a2w_ctrl = 0x00000000 }, /* unknown */
>>> + [CPRMAN_PLLA_CHANNEL_CCP2] = { .a2w_ctrl = 0x00000100 },
>>> +
>>> + [CPRMAN_PLLC_CHANNEL_CORE2] = { .a2w_ctrl = 0x00000100 },
>>> + [CPRMAN_PLLC_CHANNEL_CORE1] = { .a2w_ctrl = 0x00000100 },
>>> + [CPRMAN_PLLC_CHANNEL_PER] = { .a2w_ctrl = 0x00000002 },
>>> + [CPRMAN_PLLC_CHANNEL_CORE0] = { .a2w_ctrl = 0x00000002 },
>>> +
>>> + [CPRMAN_PLLD_CHANNEL_DSI0] = { .a2w_ctrl = 0x00000100 },
>>> + [CPRMAN_PLLD_CHANNEL_CORE] = { .a2w_ctrl = 0x00000004 },
>>> + [CPRMAN_PLLD_CHANNEL_PER] = { .a2w_ctrl = 0x00000004 },
>>> + [CPRMAN_PLLD_CHANNEL_DSI1] = { .a2w_ctrl = 0x00000100 },
>>> +
>>> + [CPRMAN_PLLH_CHANNEL_AUX] = { .a2w_ctrl = 0x00000004 },
>>> + [CPRMAN_PLLH_CHANNEL_RCAL] = { .a2w_ctrl = 0x00000000 },
>>> + [CPRMAN_PLLH_CHANNEL_PIX] = { .a2w_ctrl = 0x00000000 },
>>> +
>>> + [CPRMAN_PLLB_CHANNEL_ARM] = { .a2w_ctrl = 0x00000000 }, /* unknown */
>>> +};
>>> +
>>> +typedef struct ClockMuxResetInfo {
>>> + uint32_t cm_ctl;
>>> + uint32_t cm_div;
>>> +} ClockMuxResetInfo;
>>> +
>>> +static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] = {
>>> + [CPRMAN_CLOCK_GNRIC] = {
>>> + .cm_ctl = 0, /* unknown */
>>> + .cm_div = 0
>>> + },
>>> +
>> [...]
>>> +};
>>> +
>>> #endif
>>> diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c
>>> index 7a7401963d..7e415a017c 100644
>>> --- a/hw/misc/bcm2835_cprman.c
>>> +++ b/hw/misc/bcm2835_cprman.c
>>> @@ -51,10 +51,21 @@
>>> #include "hw/misc/bcm2835_cprman_internals.h"
>>> #include "trace.h"
>>> /* PLL */
>>> +static void pll_reset(DeviceState *dev)
>>> +{
>>> + CprmanPllState *s = CPRMAN_PLL(dev);
>>> + const PLLResetInfo *info = &PLL_RESET_INFO[s->id];
>>
>> Hmm so we overwrite various values from PLL_INIT_INFO.
>>> +
>>> + *s->reg_cm = info->cm;
>>> + *s->reg_a2w_ctrl = info->a2w_ctrl;
>>> + memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana));
>>> + *s->reg_a2w_frac = info->a2w_frac;
>>
>> set_pll_init_info() can be simplified as:
>>
>> pll->id = id;
>> pll->prediv_mask = PLL_INIT_INFO[id].prediv_mask;
>>
>> Or directly in cprman_init():
>>
>> &s->plls[i]->id = i;
>> &s->plls[i]->prediv_mask = PLL_INIT_INFO[i].prediv_mask;
>>
>> And the rest directly implemented in pll_reset().
>>
>> Maybe not, but having pll_reset() added in patch #8/15
>> "bcm2835_cprman: add a PLL channel skeleton implementation"
>> would make this patch review easier ;)
>
> Hi Phil,
>
> I think there is a misunderstanding here:
> - set_xxx_init_info functions set (among others) register pointers
> to alias the common register array "regs" in BCM2835CprmanState.
> This is really an initialization step (in the sense of the QOM
> object). Those pointers won't move during the object's lifetime.
> - xxx_reset however (like e.g. xxx_update) _dereferences_ those
> pointers to access the registers data (in this case to set their
> reset values).
>
> Doing so greatly decreases code complexity because:
> - read/write functions can directly access the common "regs" array
> without further decoding.
> - Each PLL shares a register with all its channels (A2W_CTRL). With
> this scheme, they simply all have a pointer aliasing the same data.
> - A lot a registers are unknown/unimplemented.
OK, thanks for clarifying.
(I wanted to split the boilerplate code from the dumped constants).
next prev parent reply other threads:[~2020-10-16 17:17 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-10 13:57 [PATCH v3 00/15] raspi: add the bcm2835 cprman clock manager Luc Michel
2020-10-10 13:57 ` [PATCH v3 01/15] hw/core/clock: provide the VMSTATE_ARRAY_CLOCK macro Luc Michel
2020-10-10 13:57 ` [PATCH v3 02/15] hw/core/clock: trace clock values in Hz instead of ns Luc Michel
2020-10-10 15:48 ` Philippe Mathieu-Daudé
2020-10-10 13:57 ` [PATCH v3 03/15] hw/core/clock: add the clock_new helper function Luc Michel
2020-10-10 15:17 ` Philippe Mathieu-Daudé
2020-10-10 15:44 ` Philippe Mathieu-Daudé
2020-10-10 13:57 ` [PATCH v3 04/15] hw/arm/raspi: fix CPRMAN base address Luc Michel
2020-10-10 13:57 ` [PATCH v3 05/15] hw/arm/raspi: add a skeleton implementation of the CPRMAN Luc Michel
2020-10-10 13:57 ` [PATCH v3 06/15] hw/misc/bcm2835_cprman: add a PLL skeleton implementation Luc Michel
2020-10-10 13:57 ` [PATCH v3 07/15] hw/misc/bcm2835_cprman: implement PLLs behaviour Luc Michel
2020-10-10 13:57 ` [PATCH v3 08/15] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation Luc Michel
2020-10-10 16:05 ` Philippe Mathieu-Daudé
2020-10-17 10:00 ` Philippe Mathieu-Daudé
2020-10-10 13:57 ` [PATCH v3 09/15] hw/misc/bcm2835_cprman: implement PLL channels behaviour Luc Michel
2020-10-10 13:57 ` [PATCH v3 10/15] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation Luc Michel
2020-10-10 13:57 ` [PATCH v3 11/15] hw/misc/bcm2835_cprman: implement clock mux behaviour Luc Michel
2020-10-10 15:52 ` Philippe Mathieu-Daudé
2020-10-10 13:57 ` [PATCH v3 12/15] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer Luc Michel
2020-10-10 13:57 ` [PATCH v3 13/15] hw/misc/bcm2835_cprman: add sane reset values to the registers Luc Michel
2020-10-10 16:18 ` Philippe Mathieu-Daudé
2020-10-11 18:26 ` Luc Michel
2020-10-16 17:10 ` Philippe Mathieu-Daudé [this message]
2020-10-19 15:44 ` Philippe Mathieu-Daudé
2020-10-10 13:57 ` [PATCH v3 14/15] hw/char/pl011: add a clock input Luc Michel
2020-10-10 13:57 ` [PATCH v3 15/15] hw/arm/bcm2835_peripherals: connect the UART clock Luc Michel
2020-10-16 17:11 ` [PATCH v3 00/15] raspi: add the bcm2835 cprman clock manager Philippe Mathieu-Daudé
2020-10-19 15:45 ` Peter Maydell
2020-10-19 19:31 ` Peter Maydell
2020-10-27 8:55 ` Philippe Mathieu-Daudé
2020-10-27 11:11 ` Peter Maydell
2020-10-22 22:06 ` Philippe Mathieu-Daudé
2020-10-22 22:48 ` Guenter Roeck
2020-10-23 3:55 ` Guenter Roeck
2020-10-23 11:13 ` Philippe Mathieu-Daudé
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