Re: [PATCH 03/20] target/loongarch: Add core definition

[Song Gao <gaosong@loongson.cn>]

Hi, Philippe,

On 06/29/2021 02:44 AM, Philippe Mathieu-Daudé wrote:
> On 6/28/21 2:04 PM, Song Gao wrote:
>> This patch add target state header,target definitions
>> and initialization routines.
>>
>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>> ---
>>  target/loongarch/cpu-param.h |  21 ++
>>  target/loongarch/cpu-qom.h   |  41 ++++
>>  target/loongarch/cpu.c       | 451 +++++++++++++++++++++++++++++++++++++++++++
>>  target/loongarch/cpu.h       | 245 +++++++++++++++++++++++
>>  target/loongarch/internal.h  |  74 +++++++
>>  5 files changed, 832 insertions(+)
>>  create mode 100644 target/loongarch/cpu-param.h
>>  create mode 100644 target/loongarch/cpu-qom.h
>>  create mode 100644 target/loongarch/cpu.c
>>  create mode 100644 target/loongarch/cpu.h
>>  create mode 100644 target/loongarch/internal.h
> 
>> +#define LOONGARCH_CONFIG1                                                   \
>> +((0x8 << CSR_CONF1_KSNUM_SHIFT) | (0x2f << CSR_CONF1_TMRBITS_SHIFT) |       \
>> + (0x7 << CSR_CONF1_VSMAX_SHIFT))
>> +
>> +#define LOONGARCH_CONFIG3                                                   \
>> +((0x2 << CSR_CONF3_TLBORG_SHIFT) | (0x3f << CSR_CONF3_MTLBSIZE_SHIFT) |     \
>> + (0x7 << CSR_CONF3_STLBWAYS_SHIFT) | (0x8 << CSR_CONF3_STLBIDX_SHIFT))
>> +
>> +#define LOONGARCH_MCSR0                                                     \
>> +((0x0UL << MCSR0_GR32_SHIFT) | (0x1UL << MCSR0_GR64_SHIFT) |                \
>> + (0x1UL << MCSR0_PAGING_SHIFT) | (0x1UL << MCSR0_IOCSR_SHIFT) |             \
>> + (0x2fUL << MCSR0_PABIT_SHIFT) | (0x2fUL << MCSR0_VABIT_SHIFT) |            \
>> + (0x1UL << MCSR0_UAL_SHIFT) | (0x1UL << MCSR0_RI_SHIFT) |                   \
>> + (0x1UL << MCSR0_EXEPROT_SHIFT) | (0x1UL << MCSR0_RPLVTLB_SHIFT) |          \
>> + (0x1UL << MCSR0_HUGEPG_SHIFT) | (0x1UL << MCSR0_IOCSR_BRD_SHIFT) |         \
>> + (0x0UL << MCSR0_INT_IMPL_SHIFT) | MCSR0_PRID)
>> +
>> +#define LOONGARCH_MCSR1                                                     \
>> +((0x1UL << MCSR1_FP_SHIFT) | (0x1UL << MCSR1_FPSP_SHIFT) |                  \
>> + (0x1UL << MCSR1_FPDP_SHIFT) | (0x1UL << MCSR1_FPVERS_SHIFT) |              \
>> + (0x1UL << MCSR1_LSX_SHIFT) | (0x1UL << MCSR1_LASX_SHIFT) |                 \
>> + (0x1UL << MCSR1_COMPLEX_SHIFT) | (0x1UL << MCSR1_CRYPTO_SHIFT) |           \
>> + (0x0UL << MCSR1_VZ_SHIFT) | (0x0UL << MCSR1_VZVERS_SHIFT) |                \
>> + (0x1UL << MCSR1_LLFTP_SHIFT) | (0x1UL << MCSR1_LLFTPVERS_SHIFT) |          \
>> + (0x0UL << MCSR1_X86BT_SHIFT) | (0x0UL << MCSR1_ARMBT_SHIFT) |              \
>> + (0x0UL << MCSR1_LOONGARCHBT_SHIFT) | (0x1UL << MCSR1_LSPW_SHIFT) |         \
>> + (0x1UL << MCSR1_LAMO_SHIFT) | (0x1UL << MCSR1_CCDMA_SHIFT) |               \
>> + (0x1UL << MCSR1_SFB_SHIFT) | (0x1UL << MCSR1_UCACC_SHIFT) |                \
>> + (0x1UL << MCSR1_LLEXC_SHIFT) | (0x1UL << MCSR1_SCDLY_SHIFT) |              \
>> + (0x1UL << MCSR1_LLDBAR_SHIFT) | (0x1UL << MCSR1_ITLBT_SHIFT) |             \
>> + (0x1UL << MCSR1_ICACHET_SHIFT) | (0x4UL << MCSR1_SPW_LVL_SHIFT) |          \
>> + (0x1UL << MCSR1_HPFOLD_SHIFT))
>> +
>> +#define LOONGARCH_MCSR2                                                     \
>> +((0x1UL << MCSR2_CCMUL_SHIFT) | (0x1UL << MCSR2_CCDIV_SHIFT) | CCFREQ_DEFAULT)
>> +
>> +#define LOONGARCH_MCSR3                                                     \
>> +((0x1UL << MCSR3_PMP_SHIFT) | (0x1UL << MCSR3_PAMVER_SHIFT) |               \
>> + (0x3UL << MCSR3_PMNUM_SHIFT) | (0x3fUL < MCSR3_PMBITS_SHIFT) |             \
>> + (0x1UL << MCSR3_UPM_SHIFT))
>> +
>> +
>> +#define LOONGARCH_MCSR8                                                     \
>> +((0x1UL << MCSR8_L1IUPRE_SHIFT)   | (0x0 << MCSR8_L1IUUNIFY_SHIFT) |        \
>> + (0x1UL << MCSR8_L1DPRE_SHIFT)    | (0x1UL << MCSR8_L2IUPRE_SHIFT) |        \
>> + (0x1UL << MCSR8_L2IUUNIFY_SHIFT) | (0x1UL << MCSR8_L2IUPRIV_SHIFT) |       \
>> + (0x0 << MCSR8_L2IUINCL_SHIFT)    | (0x0 << MCSR8_L2DPRE_SHIFT) |           \
>> + (0x0 << MCSR8_L2DPRIV_SHIFT)     | (0x0 << MCSR8_L2DINCL_SHIFT) |          \
>> + (0x1UL << MCSR8_L3IUPRE_SHIFT)   | (0x1UL << MCSR8_L3IUUNIFY_SHIFT) |      \
>> + (0x0 << MCSR8_L3IUPRIV_SHIFT)    | (0x1UL << MCSR8_L3IUINCL_SHIFT) |       \
>> + (0x0 << MCSR8_L3DPRE_SHIFT)      | (0x0 < MCSR8_L3DPRIV_SHIFT) |           \
>> + (0x0 << MCSR8_L3DINCL_SHIFT)     | (0x3UL << MCSR8_L1I_WAY_SHIFT) |        \
>> + (0x8UL << MCSR8_L1I_IDX_SHIFT)   | (0x6UL << MCSR8_L1I_SIZE_SHIFT))
>> +
>> +#define LOONGARCH_MCSR9                                                     \
>> +((0x3UL << MCSR9_L1D_WAY_SHIFT) | (0x8UL << MCSR9_L1D_IDX_SHIFT) |          \
>> + (0x6UL << MCSR9_L1D_SIZE_SHIFT) | (0xfUL << MCSR9_L2U_WAY_SHIFT) |         \
>> + (0x8UL << MCSR9_L2U_IDX_SHIFT) |  (0x6UL << MCSR9_L2U_SIZE_SHIFT))
>> +
>> +#define LOONGARCH_MCSR10                                                    \
>> +((0xfUL << MCSR10_L3U_WAY_SHIFT) | (0xfUL << MCSR10_L3U_IDX_SHIFT) |        \
>> + (0x6UL << MCSR10_L3U_SIZE_SHIFT))
>> +
>> +#define LOONGARCH_MCSR24                                                    \
>> +((0x0 << MCSR24_MCSRLOCK_SHIFT) | (0x0 << MCSR24_NAPEN_SHIFT) |             \
>> + (0x0 << MCSR24_VFPUCG_SHIFT) | (0x0 << MCSR24_RAMCG_SHIFT))
>> +
>> +/* LoongArch CPU definitions */
>> +const loongarch_def_t loongarch_defs[] = {
>> +    {
>> +        .name = "Loongson-3A5000",
>> +
>> +        /* for LoongArch CSR */
>> +        .CSR_PRCFG1 = LOONGARCH_CONFIG1,
>> +        .CSR_PRCFG2 = 0x3ffff000,
>> +        .CSR_PRCFG3 = LOONGARCH_CONFIG3,
>> +        .CSR_CRMD = (0 << CSR_CRMD_PLV_SHIFT) | (0 << CSR_CRMD_IE_SHIFT) |
>> +                    (1 << CSR_CRMD_DA_SHIFT) | (0 << CSR_CRMD_PG_SHIFT) |
>> +                    (1 << CSR_CRMD_DACF_SHIFT) | (1 << CSR_CRMD_DACM_SHIFT),
>> +        .CSR_ECFG = 0x7 << 16,
>> +        .CSR_STLBPGSIZE  = 0xe,
>> +        .CSR_RVACFG = 0x0,
>> +        .CSR_MCSR0 = LOONGARCH_MCSR0,
>> +        .CSR_MCSR1 = LOONGARCH_MCSR1,
>> +        .CSR_MCSR2 = LOONGARCH_MCSR2,
>> +        .CSR_MCSR3 = 0,
>> +        .CSR_MCSR8 = LOONGARCH_MCSR8,
>> +        .CSR_MCSR9 = LOONGARCH_MCSR9,
>> +        .CSR_MCSR10 = LOONGARCH_MCSR10,
>> +        .CSR_MCSR24 = LOONGARCH_MCSR24,
>> +        .FCSR0 = 0x0,
>> +        .FCSR0_MASK = 0x1f1f03df,
>> +        .PABITS = 48,
>> +        .INSN_FLAGS = CPU_LA64 | INSN_LOONGARCH,
>> +        .MMU_TYPE = MMU_TYPE_LS3A5K,
>> +    },
>> +    {
>> +        .name = "host",
>> +
>> +        /* for LoongArch CSR */
>> +        .CSR_PRCFG1 = LOONGARCH_CONFIG1,
>> +        .CSR_PRCFG2 = 0x3ffff000,
>> +        .CSR_PRCFG3 = LOONGARCH_CONFIG3,
>> +        .CSR_CRMD = (0 << CSR_CRMD_PLV_SHIFT) | (0 << CSR_CRMD_IE_SHIFT) |
>> +                    (1 << CSR_CRMD_DA_SHIFT) | (0 << CSR_CRMD_PG_SHIFT) |
>> +                    (1 << CSR_CRMD_DACF_SHIFT) | (1 << CSR_CRMD_DACM_SHIFT),
>> +        .CSR_ECFG = 0x7 << 16,
>> +        .CSR_STLBPGSIZE  = 0xe,
>> +        .CSR_RVACFG = 0x0,
>> +        .CSR_MCSR0 = LOONGARCH_MCSR0,
>> +        .CSR_MCSR1 = LOONGARCH_MCSR1,
>> +        .CSR_MCSR2 = LOONGARCH_MCSR2,
>> +        .CSR_MCSR3 = 0,
>> +        .CSR_MCSR8 = LOONGARCH_MCSR8,
>> +        .CSR_MCSR9 = LOONGARCH_MCSR9,
>> +        .CSR_MCSR10 = LOONGARCH_MCSR10,
>> +        .CSR_MCSR24 = LOONGARCH_MCSR24,
>> +        .FCSR0 = 0x0,
>> +        .FCSR0_MASK = 0x1f1f03df,
>> +        .PABITS = 48,
>> +        .INSN_FLAGS = CPU_LA64 | INSN_LOONGARCH,
>> +        .MMU_TYPE = MMU_TYPE_LS3A5K,
>> +    },
>> +};
>> +
>> +const int loongarch_defs_number = ARRAY_SIZE(loongarch_defs);
> 
> You seem to have followed the MIPS pattern we are hardly trying to
> move away. Better would be to follow the ARM pattern, which seems the
> state of the art to add new CPU features.
> 
OK, We will do it according to your suggestion.

thanks