From: Song Gao <gaosong@loongson.cn>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: peter.maydell@linaro.org, thuth@redhat.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
maobibo@loongson.cn, laurent@vivier.eu, yangxiaojuan@loongson.cn,
alistair.francis@wdc.com, pbonzini@redhat.com
Subject: Re: [PATCH 07/20] target/loongarch: Add fixed point arithmetic instruction translation
Date: Fri, 2 Jul 2021 17:16:04 +0800 [thread overview]
Message-ID: <8f1ef7ff-fa6a-972f-c460-63ee10d4a2cd@loongson.cn> (raw)
In-Reply-To: <2912e517-dba0-04f8-80e2-edc0a9b1a27d@amsat.org>
Hi, Philippe,
On 07/02/2021 04:51 PM, Philippe Mathieu-Daudé wrote:
> On 7/2/21 10:15 AM, Song Gao wrote:
>> On 07/02/2021 04:31 AM, Philippe Mathieu-Daudé wrote:
>>> On 6/28/21 2:04 PM, Song Gao wrote:
>>>> This patch implement fixed point arithemtic instruction translation.
>>>>
>>>> This includes:
>>>> - ADD.{W/D}, SUB.{W/D}
>>>> - ADDI.{W/D}, ADDU16ID
>>>> - ALSL.{W[U]/D}
>>>> - LU12I.W, LU32I.D LU52I.D
>>>> - SLT[U], SLT[U]I
>>>> - PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
>>>> - AND, OR, NOR, XOR, ANDN, ORN
>>>> - MUL.{W/D}, MULH.{W[U]/D[U]}
>>>> - MULW.D.W[U]
>>>> - DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
>>>> - ANDI, ORI, XORI
>>>>
>>>> Signed-off-by: Song Gao <gaosong@loongson.cn>
>>>> ---
>>>> target/loongarch/insns.decode | 89 ++++++++
>>>> target/loongarch/instmap.h | 53 +++++
>>>> target/loongarch/trans.inc.c | 367 +++++++++++++++++++++++++++++++++
>>>> target/loongarch/translate.c | 458 ++++++++++++++++++++++++++++++++++++++++++
>>>> 4 files changed, 967 insertions(+)
>>>> create mode 100644 target/loongarch/insns.decode
>>>> create mode 100644 target/loongarch/instmap.h
>>>> create mode 100644 target/loongarch/trans.inc.c
>
>>> It seems you are missing what decodetree is for... You should inline
>>> each opcode code from gen_loongarch_muldiv in the opcode handler.
>>>
>>> Don't take MIPS as an example =)
>>>
>> Hi, Philippe,
>>
>> I‘m not sure I understand right. Here is an example of my modification
>>
>> static bool trans_xxx(DisasContext *ctx, arg_mul_w *a)
>> {
>> gen_loongarch_muldiv(ctx, a->rd, a->rj, a->rk);
>> return true;
>> }
>> ...
>>
>> static void gen_loongarch_muldiv(DisasContext *ctx, int rd,
>> int rj, int rk)
>> {
>> TCGv t0, t1;
>>
>> if (rd == 0) {
>> /* Treat as NOP. */
>> return;
>> }
>>
>> t0 = tcg_temp_new();
>> t1 = tcg_temp_new();
>>
>> gen_load_gpr(t0, rj);
>> gen_load_gpr(t1, rk);
>>
>> switch (ctx->opcode) {
>> case xxx_opcode:
>> /* translate xxx */
>> ...
>>
>> }
>>
>> Is that right?
>
> No. With decode"tree" you only have to implement the
> decode"leaves". No need to pass 'uin32_t opcode' and
> use 'switch (ctx->opcode) ...'. Example for LA_OPC_MUL_D:
>
> static bool trans_mul_d(DisasContext *ctx, int rd, int rj, int rk)
> {
> TCGv t0, t1;
>
> check_loongarch_64(ctx);
>
> if (a->rd == 0) {
> /* Treat as NOP. */
> return true;
> }
>
> t0 = tcg_temp_new();
> t1 = tcg_temp_new();
>
> gen_load_gpr(t0, a->rj);
> gen_load_gpr(t1, a->rk);
>
> tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);
>
> tcg_temp_free(t0);
> tcg_temp_free(t1);
>
> return true;
> }
>
Got it, thanks for kindly help!
Regards
Song Gao
next prev parent reply other threads:[~2021-07-02 9:18 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-28 12:04 [PATCH 00/20] Add LoongArch linux-user emulation support Song Gao
2021-06-28 12:04 ` [PATCH 01/20] target/loongarch: Add README Song Gao
2021-06-28 18:40 ` Philippe Mathieu-Daudé
2021-06-29 7:33 ` Song Gao
2021-06-29 11:13 ` Alex Bennée
2021-06-30 1:09 ` Song Gao
2021-06-29 11:52 ` Peter Maydell
2021-06-30 1:22 ` Song Gao
2021-06-28 12:04 ` [PATCH 02/20] target/loongarch: Add CSR registers definition Song Gao
2021-06-28 12:04 ` [PATCH 03/20] target/loongarch: Add core definition Song Gao
2021-06-28 18:44 ` Philippe Mathieu-Daudé
2021-06-29 7:39 ` Song Gao
2021-06-28 12:04 ` [PATCH 04/20] target/loongarch: Add interrupt handling support Song Gao
2021-06-28 12:04 ` [PATCH 05/20] target/loongarch: Add memory management support Song Gao
2021-06-28 12:04 ` [PATCH 06/20] target/loongarch: Add main translation routines Song Gao
2021-06-28 18:46 ` Philippe Mathieu-Daudé
2021-06-29 8:50 ` Song Gao
2021-06-29 12:26 ` Alex Bennée
2021-06-30 1:04 ` Song Gao
2021-06-28 12:04 ` [PATCH 07/20] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-07-01 20:31 ` Philippe Mathieu-Daudé
2021-07-02 8:15 ` Song Gao
2021-07-02 8:51 ` Philippe Mathieu-Daudé
2021-07-02 9:16 ` Song Gao [this message]
2021-07-02 14:46 ` Richard Henderson
2021-07-05 0:45 ` Song Gao
2021-06-28 12:04 ` [PATCH 08/20] target/loongarch: Add fixed point shift " Song Gao
2021-06-28 12:04 ` [PATCH 09/20] target/loongarch: Add fixed point bit " Song Gao
2021-06-28 12:04 ` [PATCH 10/20] target/loongarch: Add fixed point load/store " Song Gao
2021-06-28 12:04 ` [PATCH 11/20] target/loongarch: Add fixed point atomic " Song Gao
2021-06-28 12:04 ` [PATCH 12/20] target/loongarch: Add fixed point extra " Song Gao
2021-06-28 12:04 ` [PATCH 13/20] target/loongarch: Add floating point arithmetic " Song Gao
2021-06-28 12:04 ` [PATCH 14/20] target/loongarch: Add floating point comparison " Song Gao
2021-06-28 12:04 ` [PATCH 15/20] target/loongarch: Add floating point conversion " Song Gao
2021-06-28 12:04 ` [PATCH 16/20] target/loongarch: Add floating point move " Song Gao
2021-06-28 12:04 ` [PATCH 17/20] target/loongarch: Add floating point load/store " Song Gao
2021-06-28 12:04 ` [PATCH 18/20] target/loongarch: Add branch " Song Gao
2021-06-28 12:04 ` [PATCH 19/20] target/loongarch: Add disassembler Song Gao
2021-06-28 12:04 ` [PATCH 20/20] target/loongarch: Add linux-user emulation support Song Gao
2021-06-29 13:42 ` Peter Maydell
2021-06-30 1:41 ` maobibo
2021-06-30 9:36 ` Alex Bennée
2021-07-01 1:07 ` maobibo
2021-07-01 6:47 ` Thomas Huth
2021-07-01 7:08 ` maobibo
2021-07-01 10:35 ` Alex Bennée
2021-07-01 10:53 ` Peter Maydell
2021-07-01 12:05 ` maobibo
2021-06-30 1:59 ` Song Gao
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