* [PATCH 0/2] target/m68k: MacOS supervisor/user mode switch fixes - part 2
@ 2022-09-25 13:48 Mark Cave-Ayland
2022-09-25 13:48 ` [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t Mark Cave-Ayland
2022-09-25 13:48 ` [PATCH 2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check Mark Cave-Ayland
0 siblings, 2 replies; 6+ messages in thread
From: Mark Cave-Ayland @ 2022-09-25 13:48 UTC (permalink / raw)
To: laurent, richard.henderson, lucienmp.qemu, qemu-devel
Here are the two outstanding patches from
https://lists.gnu.org/archive/html/qemu-devel/2022-09/msg02340.html updated and
rebased onto git master.
Patch 1 is equivalent to patch 2 in the original series but using BIT_ULL() to
set and clear the feature bits, and updating m68k_feature() to return a bool
instead of int.
Patch 2 is the same as the previous patch 3 but with Richard's R-B tag added.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Mark Cave-Ayland (2):
target/m68k: increase size of m68k CPU features from uint32_t to
uint64_t
target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr
privilege check
target/m68k/cpu.c | 9 +++++++--
target/m68k/cpu.h | 8 +++++---
target/m68k/translate.c | 2 +-
3 files changed, 13 insertions(+), 6 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t
2022-09-25 13:48 [PATCH 0/2] target/m68k: MacOS supervisor/user mode switch fixes - part 2 Mark Cave-Ayland
@ 2022-09-25 13:48 ` Mark Cave-Ayland
2022-09-25 14:43 ` Philippe Mathieu-Daudé via
2022-09-26 21:35 ` Laurent Vivier
2022-09-25 13:48 ` [PATCH 2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check Mark Cave-Ayland
1 sibling, 2 replies; 6+ messages in thread
From: Mark Cave-Ayland @ 2022-09-25 13:48 UTC (permalink / raw)
To: laurent, richard.henderson, lucienmp.qemu, qemu-devel
There are already 32 feature bits in use, so change the size of the m68k
CPU features to uint64_t (along with the associated m68k_feature()
functions) to allow up to 64 feature bits to be used.
At the same time make use of the BIT_ULL() macro when reading/writing
the CPU feature bits to improve readability, and also update m68k_feature()
to return a bool rather than an int.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
target/m68k/cpu.c | 4 ++--
target/m68k/cpu.h | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index f681be3a2a..8d23c72056 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -38,12 +38,12 @@ static bool m68k_cpu_has_work(CPUState *cs)
static void m68k_set_feature(CPUM68KState *env, int feature)
{
- env->features |= (1u << feature);
+ env->features |= BIT_ULL(feature);
}
static void m68k_unset_feature(CPUM68KState *env, int feature)
{
- env->features &= (-1u - (1u << feature));
+ env->features &= ~BIT_ULL(feature);
}
static void m68k_cpu_reset(DeviceState *dev)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 67b6c12c28..f5c6e95cb4 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -154,7 +154,7 @@ typedef struct CPUArchState {
struct {} end_reset_fields;
/* Fields from here on are preserved across CPU reset. */
- uint32_t features;
+ uint64_t features;
} CPUM68KState;
/*
@@ -539,9 +539,9 @@ enum m68k_features {
M68K_FEATURE_TRAPCC,
};
-static inline int m68k_feature(CPUM68KState *env, int feature)
+static inline bool m68k_feature(CPUM68KState *env, int feature)
{
- return (env->features & (1u << feature)) != 0;
+ return (env->features & BIT_ULL(feature)) != 0;
}
void m68k_cpu_list(void);
--
2.30.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check
2022-09-25 13:48 [PATCH 0/2] target/m68k: MacOS supervisor/user mode switch fixes - part 2 Mark Cave-Ayland
2022-09-25 13:48 ` [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t Mark Cave-Ayland
@ 2022-09-25 13:48 ` Mark Cave-Ayland
2022-09-26 21:35 ` Laurent Vivier
1 sibling, 1 reply; 6+ messages in thread
From: Mark Cave-Ayland @ 2022-09-25 13:48 UTC (permalink / raw)
To: laurent, richard.henderson, lucienmp.qemu, qemu-devel
Now that M68K_FEATURE_M68000 has been renamed to M68K_FEATURE_M68K it is easier
to see that the privilege exception check is wrong: it is currently only generated
for ColdFire CPUs when in fact it should also be generated for Motorola CPUs from
the 68010 onwards.
Introduce a new M68K_FEATURE_MOVEFROMSR_PRIV feature which is set for all non-
Motorola CPUs, and for all Motorola CPUs from the 68010 onwards and use it to
determine whether a privilege exception should be generated for the MOVE-from-SR
instruction.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/cpu.c | 5 +++++
target/m68k/cpu.h | 2 ++
target/m68k/translate.c | 2 +-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 8d23c72056..25d610db21 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -102,6 +102,7 @@ static void m5206_cpu_initfn(Object *obj)
CPUM68KState *env = &cpu->env;
m68k_set_feature(env, M68K_FEATURE_CF_ISA_A);
+ m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
}
/* Base feature set, including isns. for m68k family */
@@ -129,6 +130,7 @@ static void m68010_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_RTD);
m68k_set_feature(env, M68K_FEATURE_BKPT);
m68k_set_feature(env, M68K_FEATURE_MOVEC);
+ m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
}
/*
@@ -241,6 +243,7 @@ static void m5208_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_BRAL);
m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
m68k_set_feature(env, M68K_FEATURE_USP);
+ m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
}
static void cfv4e_cpu_initfn(Object *obj)
@@ -254,6 +257,7 @@ static void cfv4e_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_CF_FPU);
m68k_set_feature(env, M68K_FEATURE_CF_EMAC);
m68k_set_feature(env, M68K_FEATURE_USP);
+ m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
}
static void any_cpu_initfn(Object *obj)
@@ -275,6 +279,7 @@ static void any_cpu_initfn(Object *obj)
m68k_set_feature(env, M68K_FEATURE_USP);
m68k_set_feature(env, M68K_FEATURE_EXT_FULL);
m68k_set_feature(env, M68K_FEATURE_WORD_INDEX);
+ m68k_set_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV);
}
static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index f5c6e95cb4..3a9cfe2f33 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -537,6 +537,8 @@ enum m68k_features {
M68K_FEATURE_UNALIGNED_DATA,
/* TRAPcc insn. (680[2346]0, and CPU32) */
M68K_FEATURE_TRAPCC,
+ /* MOVE from SR privileged (from 68010) */
+ M68K_FEATURE_MOVEFROMSR_PRIV,
};
static inline bool m68k_feature(CPUM68KState *env, int feature)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 233b9d8e57..9df17aa4b2 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -4624,7 +4624,7 @@ DISAS_INSN(move_from_sr)
{
TCGv sr;
- if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68K)) {
+ if (IS_USER(s) && m68k_feature(env, M68K_FEATURE_MOVEFROMSR_PRIV)) {
gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE);
return;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t
2022-09-25 13:48 ` [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t Mark Cave-Ayland
@ 2022-09-25 14:43 ` Philippe Mathieu-Daudé via
2022-09-26 21:35 ` Laurent Vivier
1 sibling, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé via @ 2022-09-25 14:43 UTC (permalink / raw)
To: Mark Cave-Ayland
Cc: Laurent Vivier, Richard Henderson, Lucien Murray-Pitts,
qemu-devel@nongnu.org Developers
On Sun, Sep 25, 2022 at 3:53 PM Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> There are already 32 feature bits in use, so change the size of the m68k
> CPU features to uint64_t (along with the associated m68k_feature()
> functions) to allow up to 64 feature bits to be used.
>
> At the same time make use of the BIT_ULL() macro when reading/writing
> the CPU feature bits to improve readability, and also update m68k_feature()
> to return a bool rather than an int.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> target/m68k/cpu.c | 4 ++--
> target/m68k/cpu.h | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t
2022-09-25 13:48 ` [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t Mark Cave-Ayland
2022-09-25 14:43 ` Philippe Mathieu-Daudé via
@ 2022-09-26 21:35 ` Laurent Vivier
1 sibling, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2022-09-26 21:35 UTC (permalink / raw)
To: Mark Cave-Ayland, richard.henderson, lucienmp.qemu, qemu-devel
Le 25/09/2022 à 15:48, Mark Cave-Ayland a écrit :
> There are already 32 feature bits in use, so change the size of the m68k
> CPU features to uint64_t (along with the associated m68k_feature()
> functions) to allow up to 64 feature bits to be used.
>
> At the same time make use of the BIT_ULL() macro when reading/writing
> the CPU feature bits to improve readability, and also update m68k_feature()
> to return a bool rather than an int.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
> target/m68k/cpu.c | 4 ++--
> target/m68k/cpu.h | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
Applied to my m68k-for-7.2 branch
Thanks,
Laurent
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check
2022-09-25 13:48 ` [PATCH 2/2] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check Mark Cave-Ayland
@ 2022-09-26 21:35 ` Laurent Vivier
0 siblings, 0 replies; 6+ messages in thread
From: Laurent Vivier @ 2022-09-26 21:35 UTC (permalink / raw)
To: Mark Cave-Ayland, richard.henderson, lucienmp.qemu, qemu-devel
Le 25/09/2022 à 15:48, Mark Cave-Ayland a écrit :
> Now that M68K_FEATURE_M68000 has been renamed to M68K_FEATURE_M68K it is easier
> to see that the privilege exception check is wrong: it is currently only generated
> for ColdFire CPUs when in fact it should also be generated for Motorola CPUs from
> the 68010 onwards.
>
> Introduce a new M68K_FEATURE_MOVEFROMSR_PRIV feature which is set for all non-
> Motorola CPUs, and for all Motorola CPUs from the 68010 onwards and use it to
> determine whether a privilege exception should be generated for the MOVE-from-SR
> instruction.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/m68k/cpu.c | 5 +++++
> target/m68k/cpu.h | 2 ++
> target/m68k/translate.c | 2 +-
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
Applied to my m68k-for-7.2 branch
Thanks,
Laurent
^ permalink raw reply [flat|nested] 6+ messages in thread
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2022-09-25 13:48 ` [PATCH 1/2] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t Mark Cave-Ayland
2022-09-25 14:43 ` Philippe Mathieu-Daudé via
2022-09-26 21:35 ` Laurent Vivier
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