* [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 @ 2021-03-31 2:18 Bin Meng 2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng 2021-03-31 15:03 ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis 0 siblings, 2 replies; 6+ messages in thread From: Bin Meng @ 2021-03-31 2:18 UTC (permalink / raw) To: Alistair Francis, qemu-devel, qemu-riscv hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d2585395bf..2bad396f64 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno) static int hmode32(CPURISCVState *env, int csrno) { if (!riscv_cpu_is_32bit(env)) { - return 0; + return -RISCV_EXCP_ILLEGAL_INST; } return hmode(env, csrno); -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines 2021-03-31 2:18 [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Bin Meng @ 2021-03-31 2:18 ` Bin Meng 2021-03-31 15:51 ` Alistair Francis 2021-03-31 15:03 ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis 1 sibling, 1 reply; 6+ messages in thread From: Bin Meng @ 2021-03-31 2:18 UTC (permalink / raw) To: Alistair Francis, qemu-devel, qemu-riscv The following check: if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -RISCV_EXCP_ILLEGAL_INST; } is redundant in fflags/frm/fcsr read/write routines, as the check was already done in fs(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- target/riscv/csr.c | 24 ------------------------ 1 file changed, 24 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2bad396f64..7c24318f75 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -193,11 +193,6 @@ static int pmp(CPURISCVState *env, int csrno) /* User Floating-Point CSRs */ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = riscv_cpu_get_fflags(env); return 0; } @@ -205,9 +200,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); @@ -216,11 +208,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = env->frm; return 0; } @@ -228,9 +215,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif env->frm = val & (FSR_RD >> FSR_RD_SHIFT); @@ -239,11 +223,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { -#if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } -#endif *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); if (vs(env, csrno) >= 0) { @@ -256,9 +235,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { - return -RISCV_EXCP_ILLEGAL_INST; - } env->mstatus |= MSTATUS_FS; #endif env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines 2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng @ 2021-03-31 15:51 ` Alistair Francis 2021-06-15 9:07 ` Bin Meng 0 siblings, 1 reply; 6+ messages in thread From: Alistair Francis @ 2021-03-31 15:51 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > The following check: > > if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > return -RISCV_EXCP_ILLEGAL_INST; > } > > is redundant in fflags/frm/fcsr read/write routines, as the check was > already done in fs(). > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > target/riscv/csr.c | 24 ------------------------ > 1 file changed, 24 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 2bad396f64..7c24318f75 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -193,11 +193,6 @@ static int pmp(CPURISCVState *env, int csrno) > /* User Floating-Point CSRs */ > static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) > { > -#if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > -#endif > *val = riscv_cpu_get_fflags(env); > return 0; > } > @@ -205,9 +200,6 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) > static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) > { > #if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > env->mstatus |= MSTATUS_FS; > #endif > riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); > @@ -216,11 +208,6 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) > > static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) > { > -#if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > -#endif > *val = env->frm; > return 0; > } > @@ -228,9 +215,6 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) > static int write_frm(CPURISCVState *env, int csrno, target_ulong val) > { > #if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > env->mstatus |= MSTATUS_FS; > #endif > env->frm = val & (FSR_RD >> FSR_RD_SHIFT); > @@ -239,11 +223,6 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) > > static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) > { > -#if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > -#endif > *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) > | (env->frm << FSR_RD_SHIFT); > if (vs(env, csrno) >= 0) { > @@ -256,9 +235,6 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) > static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) > { > #if !defined(CONFIG_USER_ONLY) > - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > - return -RISCV_EXCP_ILLEGAL_INST; > - } > env->mstatus |= MSTATUS_FS; > #endif > env->frm = (val & FSR_RD) >> FSR_RD_SHIFT; > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines 2021-03-31 15:51 ` Alistair Francis @ 2021-06-15 9:07 ` Bin Meng 2021-06-15 10:42 ` Alistair Francis 0 siblings, 1 reply; 6+ messages in thread From: Bin Meng @ 2021-06-15 9:07 UTC (permalink / raw) To: Alistair Francis Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers Hi Alistair, On Wed, Mar 31, 2021 at 11:53 PM Alistair Francis <alistair23@gmail.com> wrote: > > On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > The following check: > > > > if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > > return -RISCV_EXCP_ILLEGAL_INST; > > } > > > > is redundant in fflags/frm/fcsr read/write routines, as the check was > > already done in fs(). > > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > It looks like this patch was not applied anywhere? Regards, Bin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines 2021-06-15 9:07 ` Bin Meng @ 2021-06-15 10:42 ` Alistair Francis 0 siblings, 0 replies; 6+ messages in thread From: Alistair Francis @ 2021-06-15 10:42 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers On Tue, Jun 15, 2021 at 7:07 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Alistair, > > On Wed, Mar 31, 2021 at 11:53 PM Alistair Francis <alistair23@gmail.com> wrote: > > > > On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > The following check: > > > > > > if (!env->debugger && !riscv_cpu_fp_enabled(env)) { > > > return -RISCV_EXCP_ILLEGAL_INST; > > > } > > > > > > is redundant in fflags/frm/fcsr read/write routines, as the check was > > > already done in fs(). > > > > > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > > > > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > > > > It looks like this patch was not applied anywhere? Nope, it doesn't appear to have been. Do you mind re-sending it? Alistair > > Regards, > Bin ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 2021-03-31 2:18 [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Bin Meng 2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng @ 2021-03-31 15:03 ` Alistair Francis 1 sibling, 0 replies; 6+ messages in thread From: Alistair Francis @ 2021-03-31 15:03 UTC (permalink / raw) To: Bin Meng Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers On Tue, Mar 30, 2021 at 10:18 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > hmode32() should return -RISCV_EXCP_ILLEGAL_INST for RV64. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Thanks for the patch. There is already a patch on list to fix this: "target/riscv: Fix 32-bit HS mode access permissions" Alistair > --- > > target/riscv/csr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index d2585395bf..2bad396f64 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -177,7 +177,7 @@ static int hmode(CPURISCVState *env, int csrno) > static int hmode32(CPURISCVState *env, int csrno) > { > if (!riscv_cpu_is_32bit(env)) { > - return 0; > + return -RISCV_EXCP_ILLEGAL_INST; > } > > return hmode(env, csrno); > -- > 2.25.1 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-06-15 10:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-31 2:18 [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Bin Meng 2021-03-31 2:18 ` [PATCH 2/2] target/riscv: csr: Remove redundant check in fp csr read/write routines Bin Meng 2021-03-31 15:51 ` Alistair Francis 2021-06-15 9:07 ` Bin Meng 2021-06-15 10:42 ` Alistair Francis 2021-03-31 15:03 ` [PATCH 1/2] target/riscv: csr: Fix hmode32() for RV64 Alistair Francis
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).